1 ------------------------------------------------------------------------------- 2 -- File : RawEthFramerTx.vhd 3 -- Company : SLAC National Accelerator Laboratory 4 -- Created : 2016-05-23 5 -- Last update: 2016-05-26 6 ------------------------------------------------------------------------------- 7 -- Description: Raw L2 Ethernet Framer's TX Engine 8 ------------------------------------------------------------------------------- 9 -- This file is part of 'SLAC Firmware Standard Library'. 10 -- It is subject to the license terms in the LICENSE.txt file found in the 11 -- top-level directory of this distribution and at: 12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 13 -- No part of 'SLAC Firmware Standard Library', including this file, 14 -- may be copied, modified, propagated, or distributed except according to 15 -- the terms contained in the LICENSE.txt file. 16 ------------------------------------------------------------------------------- 19 use ieee.std_logic_1164.
all;
20 use ieee.std_logic_unsigned.
all;
21 use ieee.std_logic_arith.
all;
29 --! @ingroup ethernet_RawEthFramer 33 ETH_TYPE_G : slv(15 downto 0) := x"0010");
-- 0x1000 (big-Endian configuration) 35 -- Local Configurations 36 localMac :
in slv(
47 downto 0); -- big-Endian
configuration 41 -- Interface to Ethernet Media Access Controller (MAC) 44 -- Interface to Application engine(s) 60 type RegType is record 65 wrAddr : slv(2 downto 0);
66 wrData : slv(63 downto 0);
67 rdAddr : slv(15 downto 0);
68 minByteCnt : range 0 to 64;
75 constant REG_INIT_C : RegType := ( 78 tDest => (others => '0'), 80 wrAddr => (others => '0'), 81 wrData => (others => '0'), 82 rdAddr => (others => '0'), 90 signal r : RegType := REG_INIT_C;
93 signal rdData : slv(63 downto 0);
95 -- attribute dont_touch : string; 96 -- attribute dont_touch of r : signal is "TRUE"; 97 -- attribute dont_touch of rdData : signal is "TRUE"; 108 -- Port A (Read/Write) 113 -- Port B (Read Only) 115 addrb => r.rdAddr
(2 downto 0),
119 variable v : RegType;
123 -- Latch the current value 141 ---------------------------------------------------------------------- 143 -- Check if ready to move data 147 -- Latch the routing information 159 ---------------------------------------------------------------------- 161 if (ack = '1') or (r.bcf = '1') then 166 -- Check for valid DST MAC or broadcast 167 if (remoteMac /= 0) or (r.bcf = '1') then 170 v.wrAddr := toSlv(2, 3);
171 for i in 7 downto 0 loop 172 if tKeep(i) = '1' then 175 v.wrData(7+(8*i) downto (8*i)) := x"00";
-- zero padding 178 -- Update the min. ETH Byte counter 179 v.minByteCnt := 16 + getTKeep(tKeep);
-- include header offset 199 -- Check for broadcast message 200 if (r.bcf = '1') then 206 -- Preset the address 207 v.rdAddr := toSlv(1, 16);
213 ---------------------------------------------------------------------- 215 -- Check if ready to move data 221 v.wrAddr := r.wrAddr + 1;
222 for i in 7 downto 0 loop 223 if tKeep(i) = '1' then 226 v.wrData(7+(8*i) downto (8*i)) := x"00";
-- zero padding 229 -- Update the min. ETH Byte counter 230 v.minByteCnt := r.minByteCnt + getTKeep(tKeep);
239 elsif r.wrAddr = 6 then 245 -- Check if next state is MOVE_S 246 if v.state = MOVE_S then 254 -- Check for eof during caching 260 -- Check for broadcast message 261 if (r.bcf = '1') then 266 -- Preset the address 267 v.rdAddr := toSlv(2, 16);
270 ---------------------------------------------------------------------- 272 -- Check if ready to move data 274 -- Increment the counter 275 v.rdAddr := r.rdAddr + 1;
282 -- Check for eof during caching 288 -- Check for broadcast message 289 if (r.bcf = '1') then 294 elsif r.rdAddr(15 downto 3) = 0 then 298 -- Check for eof during caching 300 -- Check for last transfer 301 if r.rdAddr(2 downto 0) = r.wrAddr then 330 ---------------------------------------------------------------------- 338 -- Register the variable for next clock cycle 349 seq :
process (
clk)
is 351 if rising_edge(clk) then 352 r <= rin after TPD_G;
in dinaslv( DATA_WIDTH_G- 1 downto 0) :=( others => '0')
AxiStreamConfigType := ssiAxiStreamConfig( 8, TKEEP_COMP_C, TUSER_FIRST_LAST_C, 8, 3) RAW_ETH_CONFIG_INIT_C
AxiStreamMasterType :=(tValid => '0',tData =>( others => '0'),tStrb =>( others => '1'),tKeep =>( others => '1'),tLast => '0',tDest =>( others => '0'),tId =>( others => '0'),tUser =>( others => '0')) AXI_STREAM_MASTER_INIT_C
out ibMacMasterAxiStreamMasterType
ADDR_WIDTH_Ginteger range 1 to ( 2** 24):= 4
ETH_TYPE_Gslv( 15 downto 0) := x"0010"
in remoteMacslv( 47 downto 0)
in addraslv( ADDR_WIDTH_G- 1 downto 0) :=( others => '0')
out tDestslv( 7 downto 0)
AxiStreamSlaveType :=(tReady => '0') AXI_STREAM_SLAVE_INIT_C
out doutbslv( DATA_WIDTH_G- 1 downto 0)
out obAppSlaveAxiStreamSlaveType
in addrbslv( ADDR_WIDTH_G- 1 downto 0) :=( others => '0')
in ibMacSlaveAxiStreamSlaveType
in obAppMasterAxiStreamMasterType
DATA_WIDTH_Ginteger range 1 to ( 2** 24):= 16
in localMacslv( 47 downto 0)