SURF  1.0
Generics | Ports | Libraries | Use Clauses
QuadPortRam Entity Reference
base » ram
+ Inheritance diagram for QuadPortRam:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
RST_POLARITY_G  sl := ' 1 '
REG_EN_G  boolean := true
MODE_G  string := " read-first "
BYTE_WR_EN_G  boolean := false
DATA_WIDTH_G  integer range 1 to ( 2 ** 24 ) := 16
BYTE_WIDTH_G  integer := 8
ADDR_WIDTH_G  integer range 1 to ( 2 ** 24 ) := 4
INIT_G  slv := " 0 "

Ports

clka   in sl := ' 0 '
en_a   in sl := ' 1 '
wea   in sl := ' 0 '
weaByte   in slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
rsta   in sl := not ( RST_POLARITY_G )
addra   in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
dina   in slv ( DATA_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
douta   out slv ( DATA_WIDTH_G - 1 downto 0 )
clkb   in sl := ' 0 '
en_b   in sl := ' 1 '
rstb   in sl := not ( RST_POLARITY_G )
addrb   in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
doutb   out slv ( DATA_WIDTH_G - 1 downto 0 )
en_c   in sl := ' 1 '
clkc   in sl := ' 0 '
rstc   in sl := not ( RST_POLARITY_G )
addrc   in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
doutc   out slv ( DATA_WIDTH_G - 1 downto 0 )
en_d   in sl := ' 1 '
clkd   in sl := ' 0 '
rstd   in sl := not ( RST_POLARITY_G )
addrd   in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
doutd   out slv ( DATA_WIDTH_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 27 of file QuadPortRam.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file QuadPortRam.vhd.

◆ RST_POLARITY_G

RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 30 of file QuadPortRam.vhd.

◆ REG_EN_G

REG_EN_G boolean := true
Generic

Definition at line 31 of file QuadPortRam.vhd.

◆ MODE_G

MODE_G string := " read-first "
Generic

Definition at line 32 of file QuadPortRam.vhd.

◆ BYTE_WR_EN_G

BYTE_WR_EN_G boolean := false
Generic

Definition at line 33 of file QuadPortRam.vhd.

◆ DATA_WIDTH_G

DATA_WIDTH_G integer range 1 to ( 2 ** 24 ) := 16
Generic

Definition at line 34 of file QuadPortRam.vhd.

◆ BYTE_WIDTH_G

BYTE_WIDTH_G integer := 8
Generic

Definition at line 35 of file QuadPortRam.vhd.

◆ ADDR_WIDTH_G

ADDR_WIDTH_G integer range 1 to ( 2 ** 24 ) := 4
Generic

Definition at line 36 of file QuadPortRam.vhd.

◆ INIT_G

INIT_G slv := " 0 "
Generic

Definition at line 37 of file QuadPortRam.vhd.

◆ clka

clka in sl := ' 0 '
Port

Definition at line 40 of file QuadPortRam.vhd.

◆ en_a

en_a in sl := ' 1 '
Port

Definition at line 41 of file QuadPortRam.vhd.

◆ wea

wea in sl := ' 0 '
Port

Definition at line 42 of file QuadPortRam.vhd.

◆ weaByte

weaByte in slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 43 of file QuadPortRam.vhd.

◆ rsta

rsta in sl := not ( RST_POLARITY_G )
Port

Definition at line 44 of file QuadPortRam.vhd.

◆ addra

addra in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 45 of file QuadPortRam.vhd.

◆ dina

dina in slv ( DATA_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 46 of file QuadPortRam.vhd.

◆ douta

douta out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 47 of file QuadPortRam.vhd.

◆ clkb

clkb in sl := ' 0 '
Port

Definition at line 49 of file QuadPortRam.vhd.

◆ en_b

en_b in sl := ' 1 '
Port

Definition at line 50 of file QuadPortRam.vhd.

◆ rstb

rstb in sl := not ( RST_POLARITY_G )
Port

Definition at line 51 of file QuadPortRam.vhd.

◆ addrb

addrb in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 52 of file QuadPortRam.vhd.

◆ doutb

doutb out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 53 of file QuadPortRam.vhd.

◆ en_c

en_c in sl := ' 1 '
Port

Definition at line 55 of file QuadPortRam.vhd.

◆ clkc

clkc in sl := ' 0 '
Port

Definition at line 56 of file QuadPortRam.vhd.

◆ rstc

rstc in sl := not ( RST_POLARITY_G )
Port

Definition at line 57 of file QuadPortRam.vhd.

◆ addrc

addrc in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 58 of file QuadPortRam.vhd.

◆ doutc

doutc out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 59 of file QuadPortRam.vhd.

◆ en_d

en_d in sl := ' 1 '
Port

Definition at line 61 of file QuadPortRam.vhd.

◆ clkd

clkd in sl := ' 0 '
Port

Definition at line 62 of file QuadPortRam.vhd.

◆ rstd

rstd in sl := not ( RST_POLARITY_G )
Port

Definition at line 63 of file QuadPortRam.vhd.

◆ addrd

addrd in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 64 of file QuadPortRam.vhd.

◆ doutd

doutd out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 65 of file QuadPortRam.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file QuadPortRam.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file QuadPortRam.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file QuadPortRam.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file QuadPortRam.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file QuadPortRam.vhd.

The documentation for this class was generated from the following file: