SURF  1.0
Pgp2bTxCell.vhd
Go to the documentation of this file.
1 -------------------------------------------------------------------------------
2 -- File : Pgp2bTxCell.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2009-05-27
5 -- Last update: 2017-03-28
6 -------------------------------------------------------------------------------
7 -- Description:
8 -- Cell Transmit interface module for the Pretty Good Protocol core.
9 -------------------------------------------------------------------------------
10 -- This file is part of 'SLAC Firmware Standard Library'.
11 -- It is subject to the license terms in the LICENSE.txt file found in the
12 -- top-level directory of this distribution and at:
13 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
14 -- No part of 'SLAC Firmware Standard Library', including this file,
15 -- may be copied, modified, propagated, or distributed except according to
16 -- the terms contained in the LICENSE.txt file.
17 -------------------------------------------------------------------------------
18 
19 LIBRARY ieee;
20 use ieee.std_logic_1164.all;
21 use ieee.std_logic_arith.all;
22 use ieee.std_logic_unsigned.all;
23 use work.StdRtlPkg.all;
24 use work.Pgp2bPkg.all;
25 
26 --! @see entity
27  --! @ingroup protocols_pgp_pgp2b_core
28 entity Pgp2bTxCell is
29  generic (
30  TPD_G : time := 1 ns;
31  TX_LANE_CNT_G : integer range 1 to 2 := 1; -- Number of bonded lanes, 1-2
32  PAYLOAD_CNT_TOP_G : integer := 7 -- Top bit for payload counter
33  );
34  port (
35 
36  -- System clock, reset & control
37  pgpTxClkEn : in sl := '1'; -- Master clock Enable
38  pgpTxClk : in sl; -- Master clock
39  pgpTxClkRst : in sl; -- Synchronous reset input
40 
41  -- Link is ready
42  pgpTxLinkReady : in sl; -- Local side has link
43 
44  -- Phy Transmit Interface
45  cellTxSOC : out sl; -- Cell data start of cell
46  cellTxSOF : out sl; -- Cell data start of frame
47  cellTxEOC : out sl; -- Cell data end of cell
48  cellTxEOF : out sl; -- Cell data end of frame
49  cellTxEOFE : out sl; -- Cell data end of frame error
50  cellTxData : out slv(TX_LANE_CNT_G*16-1 downto 0); -- Cell data data
51 
52  -- Transmit Scheduler Interface
53  schTxSOF : out sl; -- Cell contained SOF
54  schTxEOF : out sl; -- Cell contained EOF
55  schTxIdle : in sl; -- Force IDLE transmit
56  schTxReq : in sl; -- Cell transmit request
57  schTxAck : out sl; -- Cell transmit acknowledge
58  schTxTimeout : in sl; -- Cell transmit timeout
59  schTxDataVc : in slv(1 downto 0); -- Cell transmit virtual channel
60 
61  -- Frame Transmit Interface, VC 0
62  vc0FrameTxValid : in sl; -- User frame data is valid
63  vc0FrameTxReady : out sl; -- PGP is ready
64  vc0FrameTxSOF : in sl; -- User frame data start of frame
65  vc0FrameTxEOF : in sl; -- User frame data end of frame
66  vc0FrameTxEOFE : in sl; -- User frame data error
67  vc0FrameTxData : in slv(TX_LANE_CNT_G*16-1 downto 0); -- User frame data
68  vc0LocAlmostFull : in sl; -- Local buffer almost full
69  vc0LocOverflow : in sl; -- Local buffer full
70  vc0RemAlmostFull : in sl; -- Remote buffer almost full
71 
72  -- Frame Transmit Interface, VC 1
73  vc1FrameTxValid : in sl; -- User frame data is valid
74  vc1FrameTxReady : out sl; -- PGP is ready
75  vc1FrameTxSOF : in sl; -- User frame data start of frame
76  vc1FrameTxEOF : in sl; -- User frame data end of frame
77  vc1FrameTxEOFE : in sl; -- User frame data error
78  vc1FrameTxData : in slv(TX_LANE_CNT_G*16-1 downto 0); -- User frame data
79  vc1LocAlmostFull : in sl; -- Local buffer almost full
80  vc1LocOverflow : in sl; -- Local buffer full
81  vc1RemAlmostFull : in sl; -- Remote buffer almost full
82 
83  -- Frame Transmit Interface, VC 2
84  vc2FrameTxValid : in sl; -- User frame data is valid
85  vc2FrameTxReady : out sl; -- PGP is ready
86  vc2FrameTxSOF : in sl; -- User frame data start of frame
87  vc2FrameTxEOF : in sl; -- User frame data end of frame
88  vc2FrameTxEOFE : in sl; -- User frame data error
89  vc2FrameTxData : in slv(TX_LANE_CNT_G*16-1 downto 0); -- User frame data
90  vc2LocAlmostFull : in sl; -- Local buffer almost full
91  vc2LocOverflow : in sl; -- Local buffer full
92  vc2RemAlmostFull : in sl; -- Remote buffer almost full
93 
94  -- Frame Transmit Interface, VC 3
95  vc3FrameTxValid : in sl; -- User frame data is valid
96  vc3FrameTxReady : out sl; -- PGP is ready
97  vc3FrameTxSOF : in sl; -- User frame data start of frame
98  vc3FrameTxEOF : in sl; -- User frame data end of frame
99  vc3FrameTxEOFE : in sl; -- User frame data error
100  vc3FrameTxData : in slv(TX_LANE_CNT_G*16-1 downto 0); -- User frame data
101  vc3LocAlmostFull : in sl; -- Local buffer almost full
102  vc3LocOverflow : in sl; -- Local buffer full
103  vc3RemAlmostFull : in sl; -- Remote buffer almost full
104 
105  -- Transmit CRC Interface
106  crcTxIn : out slv(TX_LANE_CNT_G*16-1 downto 0); -- Transmit data for CRC
107  crcTxInit : out sl; -- Transmit CRC value init
108  crcTxValid : out sl; -- Transmit data for CRC is valid
109  crcTxOut : in slv(31 downto 0) -- Transmit calculated CRC value
110  );
111 
112 end Pgp2bTxCell;
113 
114 
115 -- Define architecture
116 architecture Pgp2bTxCell of Pgp2bTxCell is
117 
118  -- Local Signals
119  signal muxFrameTxValid : sl;
120  signal muxFrameTxSOF : sl;
121  signal muxFrameTxEOF : sl;
122  signal muxFrameTxEOFE : sl;
123  signal muxFrameTxData : slv(TX_LANE_CNT_G*16-1 downto 0);
124  signal muxRemAlmostFull : sl;
125  signal cellCnt : slv(PAYLOAD_CNT_TOP_G downto 0);
126  signal cellCntRst : sl;
127  signal nxtFrameTxReady : sl;
128  signal nxtType : slv(2 downto 0);
129  signal nxtTypeLast : slv(2 downto 0);
130  signal curTypeLast : slv(2 downto 0);
131  signal nxtTxSOF : sl;
132  signal nxtTxEOF : sl;
133  signal nxtTxAck : sl;
134  signal nxtData : slv(TX_LANE_CNT_G*16-1 downto 0);
135  signal eocWord : slv(TX_LANE_CNT_G*16-1 downto 0);
136  signal socWord : slv(TX_LANE_CNT_G*16-1 downto 0);
137  signal crcWordA : slv(TX_LANE_CNT_G*16-1 downto 0);
138  signal crcWordB : slv(TX_LANE_CNT_G*16-1 downto 0);
139  signal serialCntEn : sl;
140  signal vc0Serial : slv(5 downto 0);
141  signal vc1Serial : slv(5 downto 0);
142  signal vc2Serial : slv(5 downto 0);
143  signal vc3Serial : slv(5 downto 0);
144  signal muxSerial : slv(5 downto 0);
145  signal dly0Data : slv(TX_LANE_CNT_G*16-1 downto 0);
146  signal dly0Type : slv(2 downto 0);
147  signal dly1Data : slv(TX_LANE_CNT_G*16-1 downto 0);
148  signal dly1Type : slv(2 downto 0);
149  signal dly2Data : slv(TX_LANE_CNT_G*16-1 downto 0);
150  signal dly2Type : slv(2 downto 0);
151  signal dly3Data : slv(TX_LANE_CNT_G*16-1 downto 0);
152  signal dly3Type : slv(2 downto 0);
153  signal dly4Data : slv(TX_LANE_CNT_G*16-1 downto 0);
154  signal dly4Type : slv(2 downto 0);
155  signal int0FrameTxReady : sl;
156  signal int1FrameTxReady : sl;
157  signal int2FrameTxReady : sl;
158  signal int3FrameTxReady : sl;
159  signal intTimeout : sl;
160  signal intOverflow : slv(3 downto 0);
161 
162  -- Transmit Data Marker
163  constant TX_DATA_C : slv(2 downto 0) := "000";
164  constant TX_SOC_C : slv(2 downto 0) := "001";
165  constant TX_SOF_C : slv(2 downto 0) := "010";
166  constant TX_EOC_C : slv(2 downto 0) := "011";
167  constant TX_EOF_C : slv(2 downto 0) := "100";
168  constant TX_EOFE_C : slv(2 downto 0) := "101";
169  constant TX_CRCA_C : slv(2 downto 0) := "110";
170  constant TX_CRCB_C : slv(2 downto 0) := "111";
171 
172  -- Transmit states
173  signal curState : slv(2 downto 0);
174  signal nxtState : slv(2 downto 0);
175  constant ST_IDLE_C : slv(2 downto 0) := "001";
176  constant ST_EMPTY_C : slv(2 downto 0) := "010";
177  constant ST_SOC_C : slv(2 downto 0) := "011";
178  constant ST_DATA_C : slv(2 downto 0) := "100";
179  constant ST_CRCA_C : slv(2 downto 0) := "101";
180  constant ST_CRCB_C : slv(2 downto 0) := "110";
181  constant ST_EOC_C : slv(2 downto 0) := "111";
182 
183 begin
184 
185 
186  -- Mux incoming data
187  process ( vc0FrameTxValid, vc0FrameTxSOF, vc0FrameTxEOF, vc0FrameTxEOFE, vc0FrameTxData, vc0RemAlmostFull,
188  vc1FrameTxValid, vc1FrameTxSOF, vc1FrameTxEOF, vc1FrameTxEOFE, vc1FrameTxData, Vc1RemAlmostFull,
189  vc2FrameTxValid, vc2FrameTxSOF, vc2FrameTxEOF, vc2FrameTxEOFE, vc2FrameTxData, Vc2RemAlmostFull,
190  vc3FrameTxValid, vc3FrameTxSOF, vc3FrameTxEOF, vc3FrameTxEOFE, vc3FrameTxData, Vc3RemAlmostFull,
191  vc0Serial, vc1Serial, vc2Serial, vc3Serial, schTxDataVc ) begin
192  case schTxDataVc is
193  when "00" =>
194  muxFrameTxValid <= vc0FrameTxValid;
195  muxFrameTxSOF <= vc0FrameTxSOF;
196  muxFrameTxEOF <= vc0FrameTxEOF;
197  muxFrameTxEOFE <= vc0FrameTxEOFE;
198  muxFrameTxData <= vc0FrameTxData;
199  muxRemAlmostFull <= vc0RemAlmostFull;
200  muxSerial <= vc0Serial;
201  when "01" =>
202  muxFrameTxValid <= vc1FrameTxValid;
203  muxFrameTxSOF <= vc1FrameTxSOF;
204  muxFrameTxEOF <= vc1FrameTxEOF;
205  muxFrameTxEOFE <= vc1FrameTxEOFE;
206  muxFrameTxData <= vc1FrameTxData;
207  muxRemAlmostFull <= vc1RemAlmostFull;
208  muxSerial <= vc1Serial;
209  when "10" =>
210  muxFrameTxValid <= vc2FrameTxValid;
211  muxFrameTxSOF <= vc2FrameTxSOF;
212  muxFrameTxEOF <= vc2FrameTxEOF;
213  muxFrameTxEOFE <= vc2FrameTxEOFE;
214  muxFrameTxData <= vc2FrameTxData;
215  muxRemAlmostFull <= vc2RemAlmostFull;
216  muxSerial <= vc2Serial;
217  when others =>
218  muxFrameTxValid <= vc3FrameTxValid;
219  muxFrameTxSOF <= vc3FrameTxSOF;
220  muxFrameTxEOF <= vc3FrameTxEOF;
221  muxFrameTxEOFE <= vc3FrameTxEOFE;
222  muxFrameTxData <= vc3FrameTxData;
223  muxRemAlmostFull <= vc3RemAlmostFull;
224  muxSerial <= vc3Serial;
225  end case;
226  end process;
227 
228 
229  -- Choose data for SOF & EOF Positions
230  GEN_DATA: for i in 0 to (TX_LANE_CNT_G-1) generate
231 
232  -- SOF, vc number and serial number
233  socWord(i*16+15 downto i*16+14) <= schTxDataVc;
234  socWord(i*16+13 downto i*16+8) <= muxSerial;
235  socWord(i*16+7 downto i*16) <= (others=>'0');
236 
237  -- EOF, buffer status
238  eocWord(i*16+15 downto i*16+12) <= intOverflow;
239  eocWord(i*16+11 downto i*16+8) <= vc3LocAlmostFull & vc2LocAlmostFull & vc1LocAlmostFull & vc0LocAlmostFull;
240  eocWord(i*16+7 downto i*16) <= (others=>'0');
241  end generate;
242 
243 
244  -- Simple state machine to control transmission of data frames
245  process ( pgpTxClk ) begin
246  if rising_edge(pgpTxClk) then
247  if pgpTxClkRst = '1' then
248  curState <= ST_IDLE_C after TPD_G;
249  cellCnt <= (others=>'0') after TPD_G;
250  int0FrameTxReady <= '0' after TPD_G;
251  int1FrameTxReady <= '0' after TPD_G;
252  int2FrameTxReady <= '0' after TPD_G;
253  int3FrameTxReady <= '0' after TPD_G;
254  intTimeout <= '0' after TPD_G;
255  schTxSOF <= '0' after TPD_G;
256  schTxEOF <= '0' after TPD_G;
257  schTxAck <= '0' after TPD_G;
258  vc0Serial <= (others=>'0') after TPD_G;
259  vc1Serial <= (others=>'0') after TPD_G;
260  vc2Serial <= (others=>'0') after TPD_G;
261  vc3Serial <= (others=>'0') after TPD_G;
262  curTypeLast <= (others=>'0') after TPD_G;
263  intOverflow <= (others=>'0') after TPD_G;
264  elsif pgpTxClkEn = '1' then
265  -- State control
266  if pgpTxLinkReady = '0' then
267  curState <= ST_IDLE_C after TPD_G;
268  else
269  curState <= nxtState after TPD_G;
270  end if;
271 
272  -- Payload Counter
273  if cellCntRst = '1' then
274  cellCnt <= (others=>'1') after TPD_G;
275  elsif cellCnt /= 0 then
276  cellCnt <= cellCnt - 1 after TPD_G;
277  end if;
278 
279  -- Outgoing ready signal
280  case schTxDataVc is
281  when "00" =>
282  int0FrameTxReady <= nxtFrameTxReady after TPD_G;
283  int1FrameTxReady <= '0' after TPD_G;
284  int2FrameTxReady <= '0' after TPD_G;
285  int3FrameTxReady <= '0' after TPD_G;
286  when "01" =>
287  int0FrameTxReady <= '0' after TPD_G;
288  int1FrameTxReady <= nxtFrameTxReady after TPD_G;
289  int2FrameTxReady <= '0' after TPD_G;
290  int3FrameTxReady <= '0' after TPD_G;
291  when "10" =>
292  int0FrameTxReady <= '0' after TPD_G;
293  int1FrameTxReady <= '0' after TPD_G;
294  int2FrameTxReady <= nxtFrameTxReady after TPD_G;
295  int3FrameTxReady <= '0' after TPD_G;
296  when others =>
297  int0FrameTxReady <= '0' after TPD_G;
298  int1FrameTxReady <= '0' after TPD_G;
299  int2FrameTxReady <= '0' after TPD_G;
300  int3FrameTxReady <= nxtFrameTxReady after TPD_G;
301  end case;
302 
303  -- Register timeout request
304  if schTxReq = '1' then
305  intTimeout <= schTxTimeout after TPD_G;
306  end if;
307 
308  -- Update Last Type
309  curTypeLast <= nxtTypeLast after TPD_G;
310 
311  -- VC Serial Numbers
312  if pgpTxLinkReady = '0' then
313  vc0Serial <= (others=>'0') after TPD_G;
314  vc1Serial <= (others=>'0') after TPD_G;
315  vc2Serial <= (others=>'0') after TPD_G;
316  vc3Serial <= (others=>'0') after TPD_G;
317  elsif serialCntEn = '1' then
318  case schTxDataVc is
319  when "00" => vc0Serial <= vc0Serial + 1 after TPD_G;
320  when "01" => vc1Serial <= vc1Serial + 1 after TPD_G;
321  when "10" => vc2Serial <= vc2Serial + 1 after TPD_G;
322  when others => vc3Serial <= vc3Serial + 1 after TPD_G;
323  end case;
324  end if;
325 
326  -- Scheduler Signals
327  schTxSOF <= nxtTxSOF after TPD_G;
328  schTxEOF <= nxtTxEOF after TPD_G;
329  schTxAck <= nxtTxAck after TPD_G;
330 
331  -- Overflow Latch Until Send
332  if vc0LocOverflow = '1' then
333  intOverflow(0) <= '1' after TPD_G;
334  elsif curState = ST_EMPTY_C or curState = ST_EOC_C then
335  intOverflow(0) <= '0' after TPD_G;
336  end if;
337 
338  if vc1LocOverflow = '1' then
339  intOverflow(1) <= '1' after TPD_G;
340  elsif curState = ST_EMPTY_C or curState = ST_EOC_C then
341  intOverflow(1) <= '0' after TPD_G;
342  end if;
343 
344  if vc2LocOverflow = '1' then
345  intOverflow(2) <= '1' after TPD_G;
346  elsif curState = ST_EMPTY_C or curState = ST_EOC_C then
347  intOverflow(2) <= '0' after TPD_G;
348  end if;
349 
350  if vc3LocOverflow = '1' then
351  intOverflow(3) <= '1' after TPD_G;
352  elsif curState = ST_EMPTY_C or curState = ST_EOC_C then
353  intOverflow(3) <= '0' after TPD_G;
354  end if;
355  end if;
356  end if;
357  end process;
358 
359 
360  -- Drive TX Ready
361  vc0FrameTxReady <= int0FrameTxReady;
362  vc1FrameTxReady <= int1FrameTxReady;
363  vc2FrameTxReady <= int2FrameTxReady;
364  vc3FrameTxReady <= int3FrameTxReady;
365 
366 
367  -- Async state control
368  process ( curState, schTxIdle, schTxReq, intTimeout, cellCnt, eocWord, socWord, curTypeLast,
369  muxFrameTxValid, muxFrameTxSOF, muxFrameTxEOF, muxFrameTxEOFE, muxFrameTxData,
370  muxRemAlmostFull ) begin
371  case curState is
372 
373  -- Idle
374  when ST_IDLE_C =>
375  cellCntRst <= '1';
376  nxtFrameTxReady <= '0';
377  nxtType <= TX_DATA_C;
378  nxtData <= (others=>'0');
379  nxtTxSOF <= '0';
380  nxtTxEOF <= '0';
381  nxtTxAck <= '0';
382  serialCntEn <= '0';
383  nxtTypeLast <= (others=>'0');
384 
385  -- Idle request
386  if schTxIdle = '1' then
387  nxtState <= ST_EMPTY_C;
388 
389  -- Cell transmit request
390  elsif schTxReq = '1' then
391  nxtState <= ST_SOC_C;
392  else
393  nxtState <= curState;
394  end if;
395 
396  -- Send empty cell
397  when ST_EMPTY_C =>
398  cellCntRst <= '1';
399  nxtFrameTxReady <= '0';
400  nxtType <= TX_EOC_C;
401  nxtTxSOF <= '0';
402  nxtTxEOF <= '0';
403  nxtTxAck <= '1';
404  serialCntEn <= '0';
405  nxtData <= eocWord;
406  nxtTypeLast <= (others=>'0');
407 
408  -- Go back to idle
409  nxtState <= ST_IDLE_C;
410 
411  -- Send first charactor of cell, assert ready
412  when ST_SOC_C =>
413  cellCntRst <= '1';
414  nxtFrameTxReady <= not intTimeout;
415  nxtTxEOF <= '0';
416  nxtTxAck <= '0';
417  serialCntEn <= '0';
418  nxtData <= socWord;
419  nxtTypeLast <= (others=>'0');
420 
421  -- Determine type
422  if intTimeout = '1' then
423  nxtType <= TX_SOC_C;
424  nxtTxSOF <= '0';
425  elsif muxFrameTxSOF = '1' then
426  nxtType <= TX_SOF_C;
427  nxtTxSOF <= '1';
428  else
429  nxtType <= TX_SOC_C;
430  nxtTxSOF <= '0';
431  end if;
432 
433  -- Move on to normal data
434  nxtState <= ST_DATA_C;
435 
436  -- Send data
437  when ST_DATA_C =>
438  cellCntRst <= '0';
439  nxtTxEOF <= '0';
440  nxtTxSOF <= '0';
441  nxtTxAck <= '0';
442  serialCntEn <= '0';
443  nxtData <= muxFrameTxData;
444 
445  -- Timeout frame, force EOFE
446  if intTimeout = '1' then
447  nxtType <= TX_DATA_C;
448  nxtTypeLast <= TX_EOFE_C;
449  nxtState <= ST_CRCA_C;
450  nxtFrameTxReady <= '0';
451 
452  -- Valid is de-asserted
453  elsif muxFrameTxValid = '0' then
454  nxtTypeLast <= TX_EOC_C;
455  nxtFrameTxReady <= '0';
456  nxtType <= TX_CRCA_C;
457 
458  -- One or two CRC words?
459  if TX_LANE_CNT_G = 1 then
460  nxtState <= ST_CRCB_C;
461  else
462  nxtState <= ST_EOC_C;
463  end if;
464  else
465  nxtType <= TX_DATA_C;
466 
467  -- EOFE is asserted
468  if muxFrameTxEOFE = '1' then
469  nxtTypeLast <= TX_EOFE_C;
470  nxtState <= ST_CRCA_C;
471  nxtFrameTxReady <= '0';
472 
473  -- EOF is asserted
474  elsif muxFrameTxEOF = '1' then
475  nxtTypeLast <= TX_EOF_C;
476  nxtState <= ST_CRCA_C;
477  nxtFrameTxReady <= '0';
478 
479  -- Pause is asserted
480  elsif muxRemAlmostFull = '1' then
481  nxtTypeLast <= TX_EOC_C;
482  nxtState <= ST_CRCA_C;
483  nxtFrameTxReady <= '0';
484 
485  -- Cell size reached
486  elsif cellCnt = 0 then
487  nxtTypeLast <= TX_EOC_C;
488  nxtState <= ST_CRCA_C;
489  nxtFrameTxReady <= '0';
490 
491  -- Keep sending cell data
492  else
493  nxtTypeLast <= curTypeLast;
494  nxtState <= curState;
495  nxtFrameTxReady <= '1';
496  nxtType <= TX_DATA_C;
497  end if;
498  end if;
499 
500  -- Send CRC A
501  when ST_CRCA_C =>
502  cellCntRst <= '1';
503  nxtTxEOF <= '0';
504  nxtTxSOF <= '0';
505  nxtTxAck <= '0';
506  serialCntEn <= '0';
507  nxtData <= (others=>'0');
508  nxtType <= TX_CRCA_C;
509  nxtTypeLast <= curTypeLast;
510  nxtFrameTxReady <= '0';
511 
512  -- One or two CRC words?
513  if TX_LANE_CNT_G = 1 then
514  nxtState <= ST_CRCB_C;
515  else
516  nxtState <= ST_EOC_C;
517  end if;
518 
519  -- Send CRC B
520  when ST_CRCB_C =>
521  cellCntRst <= '1';
522  nxtTxEOF <= '0';
523  nxtTxSOF <= '0';
524  nxtTxAck <= '0';
525  serialCntEn <= '0';
526  nxtData <= (others=>'0');
527  nxtType <= TX_CRCB_C;
528  nxtTypeLast <= curTypeLast;
529  nxtFrameTxReady <= '0';
530  nxtState <= ST_EOC_C;
531 
532  -- Send End of Cell
533  when ST_EOC_C =>
534  cellCntRst <= '1';
535  nxtTxSOF <= '0';
536  nxtTxAck <= '1';
537  serialCntEn <= '1';
538  nxtData <= eocWord;
539  nxtType <= curTypeLast;
540  nxtTypeLast <= curTypeLast;
541  nxtFrameTxReady <= '0';
542  nxtState <= ST_IDLE_C;
543 
544  -- EOF?
545  if curTypeLast /= TX_EOC_C then
546  nxtTxEOF <= '1';
547  else
548  nxtTxEOF <= '0';
549  end if;
550 
551  -- Default State
552  when others =>
553  cellCntRst <= '0';
554  nxtTxEOF <= '0';
555  nxtTxSOF <= '0';
556  nxtTxAck <= '0';
557  serialCntEn <= '0';
558  nxtData <= (others=>'0');
559  nxtType <= (others=>'0');
560  nxtTypeLast <= (others=>'0');
561  nxtFrameTxReady <= '0';
562  nxtState <= ST_IDLE_C;
563  end case;
564  end process;
565 
566 
567  -- Delay chain to allow CRC data to catch up.
568  process ( pgpTxClk ) begin
569  if rising_edge(pgpTxClk) then
570  if pgpTxClkRst = '1' then
571  dly0Data <= (others=>'0');
572  dly0Type <= (others=>'0');
573  dly1Data <= (others=>'0');
574  dly1Type <= (others=>'0');
575  dly2Data <= (others=>'0');
576  dly2Type <= (others=>'0');
577  dly3Data <= (others=>'0');
578  dly3Type <= (others=>'0');
579  dly4Data <= (others=>'0');
580  dly4Type <= (others=>'0');
581  elsif pgpTxClkEn = '1' then
582  -- Delay stage 1
583  dly0Data <= nxtData after TPD_G;
584  dly0Type <= nxtType after TPD_G;
585 
586  -- Delay stage 2
587  dly1Data <= dly0Data after TPD_G;
588  dly1Type <= dly0Type after TPD_G;
589 
590  -- Delay stage 3
591  dly2Data <= dly1Data after TPD_G;
592  dly2Type <= dly1Type after TPD_G;
593 
594  -- Delay stage 3
595  dly3Data <= dly2Data after TPD_G;
596  dly3Type <= dly2Type after TPD_G;
597 
598  -- Delay stage 3
599  dly4Data <= dly3Data after TPD_G;
600  dly4Type <= dly3Type after TPD_G;
601  end if;
602  end if;
603  end process;
604 
605 
606  -- Output to CRC engine
607  crcTxIn <= dly0Data;
608  crcTxInit <= '1' when (dly0Type = TX_SOC_C or dly0Type = TX_SOF_C) else '0';
609  crcTxValid <= '1' when (dly0Type = TX_SOC_C or dly0Type = TX_SOF_C or dly0Type = TX_DATA_C) else '0';
610 
611 
612  -- CRC Data, Single lane, split into two 16-bit values
613  GEN_CRC_NARROW: if TX_LANE_CNT_G = 1 generate
614  crcWordA(7 downto 0) <= crcTxOut(31 downto 24);
615  crcWordA(15 downto 8) <= crcTxOut(23 downto 16);
616  crcWordB(7 downto 0) <= crcTxOut(15 downto 8);
617  crcWordB(15 downto 8) <= crcTxOut(7 downto 0);
618  end generate;
619 
620  -- CRC Data, Multi lane, send one 32-bit value
621  GEN_CRC_WIDE: if TX_LANE_CNT_G /= 1 generate
622  crcWordA(7 downto 0) <= crcTxOut(31 downto 24);
623  crcWordA(15 downto 8) <= crcTxOut(23 downto 16);
624  crcWordA(23 downto 16) <= crcTxOut(15 downto 8);
625  crcWordA(31 downto 24) <= crcTxOut(7 downto 0);
626  crcWordB(31 downto 0) <= (others=>'0');
627  end generate;
628 
629  -- Output stage
630  process ( pgpTxClk ) begin
631  if rising_edge(pgpTxClk) then
632  if pgpTxClkRst = '1' then
633  cellTxSOC <= '0' after TPD_G;
634  cellTxSOF <= '0' after TPD_G;
635  cellTxEOC <= '0' after TPD_G;
636  cellTxEOF <= '0' after TPD_G;
637  cellTxEOFE <= '0' after TPD_G;
638  cellTxData <= (others=>'0') after TPD_G;
639  elsif pgpTxClkEn = '1' then
640  -- Which data type
641  case dly2Type is
642  when TX_DATA_C =>
643  cellTxSOC <= '0' after TPD_G;
644  cellTxSOF <= '0' after TPD_G;
645  cellTxEOC <= '0' after TPD_G;
646  cellTxEOF <= '0' after TPD_G;
647  cellTxEOFE <= '0' after TPD_G;
648  cellTxData <= dly2Data after TPD_G;
649  when TX_SOC_C =>
650  cellTxSOC <= '1' after TPD_G;
651  cellTxSOF <= '0' after TPD_G;
652  cellTxEOC <= '0' after TPD_G;
653  cellTxEOF <= '0' after TPD_G;
654  cellTxEOFE <= '0' after TPD_G;
655  cellTxData <= dly2Data after TPD_G;
656  when TX_SOF_C =>
657  cellTxSOC <= '1' after TPD_G;
658  cellTxSOF <= '1' after TPD_G;
659  cellTxEOC <= '0' after TPD_G;
660  cellTxEOF <= '0' after TPD_G;
661  cellTxEOFE <= '0' after TPD_G;
662  cellTxData <= dly2Data after TPD_G;
663  when TX_CRCA_C =>
664  cellTxSOC <= '0' after TPD_G;
665  cellTxSOF <= '0' after TPD_G;
666  cellTxEOC <= '0' after TPD_G;
667  cellTxEOF <= '0' after TPD_G;
668  cellTxEOFE <= '0' after TPD_G;
669  cellTxData <= crcWordA after TPD_G;
670  when TX_CRCB_C =>
671  cellTxSOC <= '0' after TPD_G;
672  cellTxSOF <= '0' after TPD_G;
673  cellTxEOC <= '0' after TPD_G;
674  cellTxEOF <= '0' after TPD_G;
675  cellTxEOFE <= '0' after TPD_G;
676  cellTxData <= crcWordB after TPD_G;
677  when TX_EOC_C =>
678  cellTxSOC <= '0' after TPD_G;
679  cellTxSOF <= '0' after TPD_G;
680  cellTxEOC <= '1' after TPD_G;
681  cellTxEOF <= '0' after TPD_G;
682  cellTxEOFE <= '0' after TPD_G;
683  cellTxData <= dly2Data after TPD_G;
684  when TX_EOF_C =>
685  cellTxSOC <= '0' after TPD_G;
686  cellTxSOF <= '0' after TPD_G;
687  cellTxEOC <= '1' after TPD_G;
688  cellTxEOF <= '1' after TPD_G;
689  cellTxEOFE <= '0' after TPD_G;
690  cellTxData <= dly2Data after TPD_G;
691  when TX_EOFE_C =>
692  cellTxSOC <= '0' after TPD_G;
693  cellTxSOF <= '0' after TPD_G;
694  cellTxEOC <= '1' after TPD_G;
695  cellTxEOF <= '1' after TPD_G;
696  cellTxEOFE <= '1' after TPD_G;
697  cellTxData <= dly2Data after TPD_G;
698  when others =>
699  cellTxSOC <= '0' after TPD_G;
700  cellTxSOF <= '0' after TPD_G;
701  cellTxEOC <= '0' after TPD_G;
702  cellTxEOF <= '0' after TPD_G;
703  cellTxEOFE <= '0' after TPD_G;
704  cellTxData <= (others=>'0') after TPD_G;
705  end case;
706  end if;
707  end if;
708  end process;
709 
710 end Pgp2bTxCell;
711 
Pgp2bTxCell.Pgp2bTxCell.nxtTypeLast
slv( 2 downto 0) nxtTypeLast
Definition: Pgp2bTxCell.vhd:129
Pgp2bTxCell.crcTxValid
out crcTxValidsl
Definition: Pgp2bTxCell.vhd:108
Pgp2bTxCell.Pgp2bTxCell.vc0Serial
slv( 5 downto 0) vc0Serial
Definition: Pgp2bTxCell.vhd:140
Pgp2bTxCell.Pgp2bTxCell.eocWord
slv( TX_LANE_CNT_G* 16- 1 downto 0) eocWord
Definition: Pgp2bTxCell.vhd:135
Pgp2bTxCell.pgpTxLinkReady
in pgpTxLinkReadysl
Definition: Pgp2bTxCell.vhd:42
Pgp2bTxCell.Pgp2bTxCell.nxtData
slv( TX_LANE_CNT_G* 16- 1 downto 0) nxtData
Definition: Pgp2bTxCell.vhd:134
Pgp2bTxCell.schTxSOF
out schTxSOFsl
Definition: Pgp2bTxCell.vhd:53
Pgp2bTxCell.vc2FrameTxEOFE
in vc2FrameTxEOFEsl
Definition: Pgp2bTxCell.vhd:88
Pgp2bTxCell.vc3FrameTxData
in vc3FrameTxDataslv( TX_LANE_CNT_G* 16- 1 downto 0)
Definition: Pgp2bTxCell.vhd:100
Pgp2bTxCell.Pgp2bTxCell.ST_CRCB_C
slv( 2 downto 0) := "110" ST_CRCB_C
Definition: Pgp2bTxCell.vhd:180
Pgp2bTxCell.schTxEOF
out schTxEOFsl
Definition: Pgp2bTxCell.vhd:54
Pgp2bTxCell.Pgp2bTxCell.dly2Data
slv( TX_LANE_CNT_G* 16- 1 downto 0) dly2Data
Definition: Pgp2bTxCell.vhd:149
Pgp2bTxCell.Pgp2bTxCell.TX_CRCA_C
slv( 2 downto 0) := "110" TX_CRCA_C
Definition: Pgp2bTxCell.vhd:169
Pgp2bTxCell.Pgp2bTxCell.curState
slv( 2 downto 0) curState
Definition: Pgp2bTxCell.vhd:173
Pgp2bTxCell.cellTxSOC
out cellTxSOCsl
Definition: Pgp2bTxCell.vhd:45
Pgp2bTxCell.Pgp2bTxCell.nxtState
slv( 2 downto 0) nxtState
Definition: Pgp2bTxCell.vhd:174
Pgp2bTxCell.crcTxIn
out crcTxInslv( TX_LANE_CNT_G* 16- 1 downto 0)
Definition: Pgp2bTxCell.vhd:106
Pgp2bTxCell.Pgp2bTxCell.vc3Serial
slv( 5 downto 0) vc3Serial
Definition: Pgp2bTxCell.vhd:143
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
Pgp2bTxCell.vc0RemAlmostFull
in vc0RemAlmostFullsl
Definition: Pgp2bTxCell.vhd:70
Pgp2bTxCell.Pgp2bTxCell.curTypeLast
slv( 2 downto 0) curTypeLast
Definition: Pgp2bTxCell.vhd:130
Pgp2bTxCell.vc2LocAlmostFull
in vc2LocAlmostFullsl
Definition: Pgp2bTxCell.vhd:90
Pgp2bTxCell.vc1FrameTxSOF
in vc1FrameTxSOFsl
Definition: Pgp2bTxCell.vhd:75
Pgp2bTxCell.Pgp2bTxCell.TX_EOFE_C
slv( 2 downto 0) := "101" TX_EOFE_C
Definition: Pgp2bTxCell.vhd:168
Pgp2bTxCell.Pgp2bTxCell.vc2Serial
slv( 5 downto 0) vc2Serial
Definition: Pgp2bTxCell.vhd:142
Pgp2bTxCell.vc2FrameTxEOF
in vc2FrameTxEOFsl
Definition: Pgp2bTxCell.vhd:87
Pgp2bTxCell.Pgp2bTxCell.crcWordB
slv( TX_LANE_CNT_G* 16- 1 downto 0) crcWordB
Definition: Pgp2bTxCell.vhd:138
Pgp2bTxCell.vc1FrameTxData
in vc1FrameTxDataslv( TX_LANE_CNT_G* 16- 1 downto 0)
Definition: Pgp2bTxCell.vhd:78
Pgp2bTxCell.pgpTxClkEn
in pgpTxClkEnsl := '1'
Definition: Pgp2bTxCell.vhd:37
Pgp2bTxCell.Pgp2bTxCell.ST_IDLE_C
slv( 2 downto 0) := "001" ST_IDLE_C
Definition: Pgp2bTxCell.vhd:175
Pgp2bTxCell.Pgp2bTxCell.TX_DATA_C
slv( 2 downto 0) := "000" TX_DATA_C
Definition: Pgp2bTxCell.vhd:163
Pgp2bTxCell.vc2FrameTxData
in vc2FrameTxDataslv( TX_LANE_CNT_G* 16- 1 downto 0)
Definition: Pgp2bTxCell.vhd:89
Pgp2bTxCell.Pgp2bTxCell.ST_CRCA_C
slv( 2 downto 0) := "101" ST_CRCA_C
Definition: Pgp2bTxCell.vhd:179
Pgp2bTxCell.vc2FrameTxReady
out vc2FrameTxReadysl
Definition: Pgp2bTxCell.vhd:85
Pgp2bTxCell.vc1RemAlmostFull
in vc1RemAlmostFullsl
Definition: Pgp2bTxCell.vhd:81
Pgp2bTxCell.schTxDataVc
in schTxDataVcslv( 1 downto 0)
Definition: Pgp2bTxCell.vhd:59
Pgp2bTxCell.vc3RemAlmostFull
in vc3RemAlmostFullsl
Definition: Pgp2bTxCell.vhd:103
Pgp2bTxCell.Pgp2bTxCell.dly0Type
slv( 2 downto 0) dly0Type
Definition: Pgp2bTxCell.vhd:146
Pgp2bTxCell.cellTxData
out cellTxDataslv( TX_LANE_CNT_G* 16- 1 downto 0)
Definition: Pgp2bTxCell.vhd:50
Pgp2bTxCell.Pgp2bTxCell.crcWordA
slv( TX_LANE_CNT_G* 16- 1 downto 0) crcWordA
Definition: Pgp2bTxCell.vhd:137
Pgp2bTxCell.Pgp2bTxCell.TX_EOF_C
slv( 2 downto 0) := "100" TX_EOF_C
Definition: Pgp2bTxCell.vhd:167
Pgp2bTx.ieee
_library_ ieeeieee
Definition: Pgp2bTx.vhd:19
Pgp2bTxCell.Pgp2bTxCell.muxSerial
slv( 5 downto 0) muxSerial
Definition: Pgp2bTxCell.vhd:144
Pgp2bTxCell.PAYLOAD_CNT_TOP_G
PAYLOAD_CNT_TOP_Ginteger := 7
Definition: Pgp2bTxCell.vhd:33
Pgp2bTxCell.Pgp2bTxCell.intOverflow
slv( 3 downto 0) intOverflow
Definition: Pgp2bTxCell.vhd:160
Pgp2bTxCell.vc0LocAlmostFull
in vc0LocAlmostFullsl
Definition: Pgp2bTxCell.vhd:68
Pgp2bTxCell.Pgp2bTxCell.ST_EMPTY_C
slv( 2 downto 0) := "010" ST_EMPTY_C
Definition: Pgp2bTxCell.vhd:176
Pgp2bTxCell.Pgp2bTxCell.vc1Serial
slv( 5 downto 0) vc1Serial
Definition: Pgp2bTxCell.vhd:141
Pgp2bTxCell.cellTxSOF
out cellTxSOFsl
Definition: Pgp2bTxCell.vhd:46
Pgp2bTxCell.vc2FrameTxValid
in vc2FrameTxValidsl
Definition: Pgp2bTxCell.vhd:84
Pgp2bTxCell.TPD_G
TPD_Gtime := 1 ns
Definition: Pgp2bTxCell.vhd:30
Pgp2bTxCell.vc1FrameTxReady
out vc1FrameTxReadysl
Definition: Pgp2bTxCell.vhd:74
Pgp2bTxCell.Pgp2bTxCell.dly3Data
slv( TX_LANE_CNT_G* 16- 1 downto 0) dly3Data
Definition: Pgp2bTxCell.vhd:151
Pgp2bTxCell.pgpTxClkRst
in pgpTxClkRstsl
Definition: Pgp2bTxCell.vhd:39
Pgp2bTxCell.cellTxEOF
out cellTxEOFsl
Definition: Pgp2bTxCell.vhd:48
Pgp2bTxCell.schTxReq
in schTxReqsl
Definition: Pgp2bTxCell.vhd:56
Pgp2bTxCell.schTxAck
out schTxAcksl
Definition: Pgp2bTxCell.vhd:57
Pgp2bTxCell.Pgp2bTxCell.TX_CRCB_C
slv( 2 downto 0) := "111" TX_CRCB_C
Definition: Pgp2bTxCell.vhd:170
Pgp2bTxCell.vc0FrameTxValid
in vc0FrameTxValidsl
Definition: Pgp2bTxCell.vhd:62
Pgp2bTxCell.Pgp2bTxCell.ST_DATA_C
slv( 2 downto 0) := "100" ST_DATA_C
Definition: Pgp2bTxCell.vhd:178
Pgp2bTxCell.vc1FrameTxEOF
in vc1FrameTxEOFsl
Definition: Pgp2bTxCell.vhd:76
Pgp2bTxCell.Pgp2bTxCell.muxFrameTxData
slv( TX_LANE_CNT_G* 16- 1 downto 0) muxFrameTxData
Definition: Pgp2bTxCell.vhd:123
Pgp2bTxCell.vc3FrameTxEOF
in vc3FrameTxEOFsl
Definition: Pgp2bTxCell.vhd:98
Pgp2bTxCell.vc3LocOverflow
in vc3LocOverflowsl
Definition: Pgp2bTxCell.vhd:102
Pgp2bTxCell.cellTxEOC
out cellTxEOCsl
Definition: Pgp2bTxCell.vhd:47
Pgp2bTxCell.Pgp2bTxCell.ST_SOC_C
slv( 2 downto 0) := "011" ST_SOC_C
Definition: Pgp2bTxCell.vhd:177
Pgp2bTxCell.vc0FrameTxEOFE
in vc0FrameTxEOFEsl
Definition: Pgp2bTxCell.vhd:66
Pgp2bTxCell.vc1LocAlmostFull
in vc1LocAlmostFullsl
Definition: Pgp2bTxCell.vhd:79
Pgp2bTxCell.vc1FrameTxValid
in vc1FrameTxValidsl
Definition: Pgp2bTxCell.vhd:73
Pgp2bTxCell.Pgp2bTxCell.dly2Type
slv( 2 downto 0) dly2Type
Definition: Pgp2bTxCell.vhd:150
Pgp2bTxCell.Pgp2bTxCell.socWord
slv( TX_LANE_CNT_G* 16- 1 downto 0) socWord
Definition: Pgp2bTxCell.vhd:136
Pgp2bTxCell.Pgp2bTxCell.TX_SOF_C
slv( 2 downto 0) := "010" TX_SOF_C
Definition: Pgp2bTxCell.vhd:165
Pgp2bTxCell.vc3LocAlmostFull
in vc3LocAlmostFullsl
Definition: Pgp2bTxCell.vhd:101
Pgp2bTxCell.vc3FrameTxSOF
in vc3FrameTxSOFsl
Definition: Pgp2bTxCell.vhd:97
Pgp2bTxCell.Pgp2bTxCell.cellCnt
slv( PAYLOAD_CNT_TOP_G downto 0) cellCnt
Definition: Pgp2bTxCell.vhd:125
Pgp2bTxCell.Pgp2bTxCell.TX_EOC_C
slv( 2 downto 0) := "011" TX_EOC_C
Definition: Pgp2bTxCell.vhd:166
Pgp2bTxCell.Pgp2bTxCell.nxtType
slv( 2 downto 0) nxtType
Definition: Pgp2bTxCell.vhd:128
Pgp2bTxCell.vc2RemAlmostFull
in vc2RemAlmostFullsl
Definition: Pgp2bTxCell.vhd:92
Pgp2bTxCell.Pgp2bTxCell.ST_EOC_C
slv( 2 downto 0) := "111" ST_EOC_C
Definition: Pgp2bTxCell.vhd:181
Pgp2bTxCell.vc2LocOverflow
in vc2LocOverflowsl
Definition: Pgp2bTxCell.vhd:91
Pgp2bTxCell.Pgp2bTxCell.dly0Data
slv( TX_LANE_CNT_G* 16- 1 downto 0) dly0Data
Definition: Pgp2bTxCell.vhd:145
Pgp2bTxCell.vc0FrameTxReady
out vc0FrameTxReadysl
Definition: Pgp2bTxCell.vhd:63
Pgp2bTxCell.schTxTimeout
in schTxTimeoutsl
Definition: Pgp2bTxCell.vhd:58
Pgp2bTxCell.vc0FrameTxEOF
in vc0FrameTxEOFsl
Definition: Pgp2bTxCell.vhd:65
Pgp2bTxCell.vc0FrameTxSOF
in vc0FrameTxSOFsl
Definition: Pgp2bTxCell.vhd:64
Pgp2bTxCell.Pgp2bTxCell.dly1Data
slv( TX_LANE_CNT_G* 16- 1 downto 0) dly1Data
Definition: Pgp2bTxCell.vhd:147
Pgp2bTxCell.TX_LANE_CNT_G
TX_LANE_CNT_Ginteger range 1 to 2:= 1
Definition: Pgp2bTxCell.vhd:31
Pgp2bTxCell.vc0LocOverflow
in vc0LocOverflowsl
Definition: Pgp2bTxCell.vhd:69
Pgp2bTxCell.crcTxInit
out crcTxInitsl
Definition: Pgp2bTxCell.vhd:107
Pgp2bTxCell.vc3FrameTxValid
in vc3FrameTxValidsl
Definition: Pgp2bTxCell.vhd:95
Pgp2bTxCell.Pgp2bTxCell.dly1Type
slv( 2 downto 0) dly1Type
Definition: Pgp2bTxCell.vhd:148
Pgp2bTxCell.vc1LocOverflow
in vc1LocOverflowsl
Definition: Pgp2bTxCell.vhd:80
Pgp2bTxCell.pgpTxClk
in pgpTxClksl
Definition: Pgp2bTxCell.vhd:38
Pgp2bTxCell.vc0FrameTxData
in vc0FrameTxDataslv( TX_LANE_CNT_G* 16- 1 downto 0)
Definition: Pgp2bTxCell.vhd:67
Pgp2bTxCell.Pgp2bTxCell.dly3Type
slv( 2 downto 0) dly3Type
Definition: Pgp2bTxCell.vhd:152
Pgp2bTxCell.Pgp2bTxCell.dly4Type
slv( 2 downto 0) dly4Type
Definition: Pgp2bTxCell.vhd:154
Pgp2bTxCell.vc3FrameTxReady
out vc3FrameTxReadysl
Definition: Pgp2bTxCell.vhd:96
Pgp2bTxCell.crcTxOut
in crcTxOutslv( 31 downto 0)
Definition: Pgp2bTxCell.vhd:110
Pgp2bTxCell.schTxIdle
in schTxIdlesl
Definition: Pgp2bTxCell.vhd:55
Pgp2bTxCell.vc2FrameTxSOF
in vc2FrameTxSOFsl
Definition: Pgp2bTxCell.vhd:86
Pgp2bTxCell.cellTxEOFE
out cellTxEOFEsl
Definition: Pgp2bTxCell.vhd:49
Pgp2bTxCell.vc3FrameTxEOFE
in vc3FrameTxEOFEsl
Definition: Pgp2bTxCell.vhd:99
Pgp2bTxCell.Pgp2bTxCell.dly4Data
slv( TX_LANE_CNT_G* 16- 1 downto 0) dly4Data
Definition: Pgp2bTxCell.vhd:153
Pgp2bTxCell.Pgp2bTxCell.TX_SOC_C
slv( 2 downto 0) := "001" TX_SOC_C
Definition: Pgp2bTxCell.vhd:164
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
Pgp2bTxCell.vc1FrameTxEOFE
in vc1FrameTxEOFEsl
Definition: Pgp2bTxCell.vhd:77