SURF  1.0
GtpDualFixedLatCore.vhd
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1 -------------------------------------------------------------------------------
2 -- File : GtpDualFixedLatCore.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2012-11-28
5 -- Last update: 2013-08-02
6 -------------------------------------------------------------------------------
7 -- Description: Pgp2 Gtp Low Latency Core
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 library UNISIM;
21 use UNISIM.VCOMPONENTS.all;
22 use work.StdRtlPkg.all;
23 
24 --! @see entity
25  --! @ingroup xilinx_Virtex5_gtp
26 entity GtpDualFixedLatCore is
27  generic (
28  TPD_G : time := 1 ns;
29 
30  -- GTP Parameters
31  SIM_PLL_PERDIV2 : bit_vector := X"0C8"; -- "011001000";
32  CLK25_DIVIDER : integer := 5;
33  PLL_DIVSEL_FB : integer := 2;
34  PLL_DIVSEL_REF : integer := 1;
35 
36  -- Recovered clock parameters
37  REC_CLK_PERIOD : real := 4.000;
38  REC_PLL_MULT : integer := 4;
39  REC_PLL_DIV : integer := 1
40  );
41  port (
42 
43  -- GTP Signals
44  gtpClkIn : in std_logic; -- GTP Reference Clock In
45  gtpRefClkOut : out std_logic; -- GTP Reference Clock Output
46  gtpRxN : in slv(1 downto 0); -- GTP Serial Receive Negative
47  gtpRxP : in slv(1 downto 0); -- GTP Serial Receive Positive
48  gtpTxN : out slv(1 downto 0); -- GTP Serial Transmit Negative
49  gtpTxP : out slv(1 downto 0); -- GTP Serial Transmit Positive
50 
51  -- Shared
52  gtpReset : in std_logic;
53  gtpResetDone : out slv(1 downto 0);
54  gtpPllLockDet : out std_logic;
55  gtpLoopback : in slv(1 downto 0);
56 
57  -- Rx Resets
58  gtpRxReset : in slv(1 downto 0);
59  gtpRxCdrReset : in slv(1 downto 0);
60  gtpRxElecIdle : out slv(1 downto 0);
61  gtpRxElecIdleRst : in slv(1 downto 0);
62 
63  -- Rx Clocks
64  gtpRxUsrClk : out slv(1 downto 0); -- 1 byte clock (recovered)
65  gtpRxUsrClk2 : out slv(1 downto 0); -- 2 byte clock (recovered)
66  gtpRxUsrClkRst : out slv(1 downto 0); -- Reset for 2 byte clock
67 
68  -- Rx Data
69  gtpRxData : out slv16Array(1 downto 0);
70  gtpRxDataK : out slv2Array(1 downto 0);
71  gtpRxDecErr : out slv2Array(1 downto 0);
72  gtpRxDispErr : out slv2Array(1 downto 0);
73  gtpRxPolarity : in slv(1 downto 0);
74  gtpRxAligned : out slv(1 downto 0);
75 
76  -- Tx Resets
77  gtpTxReset : in slv(1 downto 0);
78 
79  -- Tx Clocks
80  gtpTxUsrClk : in std_logic;
81  gtpTxUsrClk2 : in std_logic;
82 
83  gtpTxAligned : out std_logic;
84 
85  -- Tx Data
86  gtpTxData : in slv16Array(1 downto 0);
87  gtpTxDataK : in slv2Array(1 downto 0)
88  );
89 
90 end GtpDualFixedLatCore;
91 
92 architecture rtl of GtpDualFixedLatCore is
93 
94  signal gtpPllLockDetInt : std_logic;
95  signal tmpRefClkOut : std_logic;
96 
97  --------------------------------------------------------------------------------------------------
98  -- Rx Signals
99  --------------------------------------------------------------------------------------------------
100  -- Clocking
101  signal gtpRxRecClk : slv(1 downto 0); -- Raw rxrecclk from GTP, not square, needs DCM or PLL
102  signal gtpRxRecClkBufG : slv(1 downto 0);
103  signal rxRecClkPllOut0 : slv(1 downto 0); -- 1 byte clock
104  signal rxRecClkPllOut1 : slv(1 downto 0); -- 2 byte clock
105  signal rxRecClkPllOut2 : slv(1 downto 0); -- 2 byte clock (180 deg phase shift)
106  signal rxRecClkPllFbIn : slv(1 downto 0);
107  signal rxRecClkPllFbOut : slv(1 downto 0);
108  signal rxRecClkPllLocked : slv(1 downto 0);
109  signal rxUsrClk2Sel : slv(1 downto 0); -- Selects which 2 byte clock is used
110  signal gtpRxUsrClkInt : slv(1 downto 0);
111  signal gtpRxUsrClk2Int : slv(1 downto 0);
112  signal gtpRxUsrClkRstInt : slv(1 downto 0);
113 
114  -- Rx Data
115  signal gtpRxDataRaw : slv20Array(1 downto 0);
116  signal gtpRxDecErrInt : slv2Array(1 downto 0);
117  signal gtpRxDispErrInt : slv2Array(1 downto 0);
118 
119  -- Rx Phase Alignment
120  signal gtpRxSlide : slv(1 downto 0);
121 
122  -- Tx Phase Alignment
123  signal gtpTxEnPmaPhaseAlign : std_logic;
124  signal gtpTxPmaSetPhase : std_logic;
125 
126  -- Resets
127  signal gtpRxCdrResetFinal : slv(1 downto 0);
128  signal rxCommaAlignReset : slv(1 downto 0);
129 
130 begin
131 
132  DUAL_INST_LOOP : for i in 1 downto 0 generate
133 
134 
135  --------------------------------------------------------------------------------------------------
136  -- Rx Data Path
137  --------------------------------------------------------------------------------------------------
138  RX_REC_CLK_BUFG : BUFG
139  port map (
140  O => gtpRxRecClkBufG(i), -- Feeds pll clkin
141  I => gtpRxRecClk(i)); -- From GTP RXRECCLK
142 
143  RX_REC_CLK_PLL : PLL_BASE
144  generic map(
145  BANDWIDTH => "OPTIMIZED",
146  CLKIN_PERIOD => REC_CLK_PERIOD,
147  CLKOUT0_DIVIDE => REC_PLL_MULT,
148  CLKOUT1_DIVIDE => REC_PLL_MULT * 2 ,
149  CLKOUT2_DIVIDE => REC_PLL_MULT * 2 ,
150  CLKOUT0_PHASE => 0.000,
151  CLKOUT1_PHASE => 0.000,
152  CLKOUT2_PHASE => 180.000,
153  CLKOUT0_DUTY_CYCLE => 0.500,
154  CLKOUT1_DUTY_CYCLE => 0.500,
155  CLKOUT2_DUTY_CYCLE => 0.500,
156  COMPENSATION => "SYSTEM_SYNCHRONOUS",
157  DIVCLK_DIVIDE => REC_PLL_DIV,
158  CLKFBOUT_MULT => REC_PLL_MULT,
159  CLKFBOUT_PHASE => 0.0,
160  REF_JITTER => 0.005000)
161  port map (
162  CLKFBIN => rxRecClkPllFbIn(i),
163  CLKIN => gtpRxRecClkBufG(i),
164  RST => '0',
165  CLKFBOUT => rxRecClkPllFbOut(i),
166  CLKOUT0 => rxRecClkPllOut0(i),
167  CLKOUT1 => rxRecClkPllOut1(i),
168  CLKOUT2 => rxRecClkPllOut2(i),
169  CLKOUT3 => open,
170  CLKOUT4 => open,
171  CLKOUT5 => open,
172  LOCKED => rxRecClkPllLocked(i));
173 
174  -- Feedback for PLL
175  RX_REC_CLK_PLL_FB_BUFG : BUFG
176  port map (
177  O => rxRecClkPllFbIn(i),
178  I => rxRecClkPllFbOut(i));
179 
180  -- Buffer pll outputs
181  RX_USR_CLK_BUFG : BUFG
182  port map (
183  I => rxRecClkPllOut0(i),
184  O => gtpRxUsrClkInt(i));
185 
186  RX_USR_CLK2_BUFMUX : BUFGMUX_CTRL
187  port map (
188  I1 => rxRecClkPllOut1(i),
189  I0 => rxRecClkPllOut2(i),
190  S => rxUsrClk2Sel(i),
191  O => gtpRxUsrClk2Int(i));
192 
193  RstSync_1 : entity work.RstSync
194  generic map (
195  TPD_G => TPD_G,
196  IN_POLARITY_G => '0',
197  OUT_POLARITY_G => '1',
198  RELEASE_DELAY_G => 3)
199  port map (
200  clk => gtpRxUsrClk2Int(i),
201  asyncRst => rxRecClkPllLocked(i),
202  syncRst => gtpRxUsrClkRstInt(i));
203 
204  -- Output recovered clocks for external use
205  gtpRxUsrClk2(i) <= gtpRxUsrClk2Int(i);
206  gtpRxUsrClk(i) <= gtpRxUsrClkInt(i);
207  gtpRxUsrClkRst(i) <= gtpRxUsrClkRstInt(i);
208 
209  -- Comma aligner and RxRst modules both drive CDR Reset
210  gtpRxCdrResetFinal(i) <= gtpRxCdrReset(i) or rxCommaAlignReset(i);
211 
212  -- Manual comma aligner
213  GtpRxCommaAligner_1 : entity work.GtpRxCommaAligner
214  generic map (
215  TPD_G => TPD_G)
216  port map (
217  gtpRxUsrClk2 => gtpRxUsrClk2Int(i),
218  gtpRxUsrClk2Rst => gtpRxUsrClkRstInt(i),
219  gtpRxData => gtpRxDataRaw(i),
220  codeErr => gtpRxDecErrInt(i),
221  dispErr => gtpRxDispErrInt(i),
222  gtpRxUsrClk2Sel => rxUsrClk2Sel(i),
223  gtpRxSlide => gtpRxSlide(i),
224  gtpRxCdrReset => rxCommaAlignReset(i),
225  aligned => gtpRxAligned(i));
226 
227  Decoder8b10b_1 : entity work.Decoder8b10b
228  generic map (
229  TPD_G => TPD_G,
230  NUM_BYTES_G => 2,
231  RST_POLARITY_G => '1',
232  RST_ASYNC_G => true)
233  port map (
234  clk => gtpRxUsrClk2Int(i),
235  rst => gtpRxUsrClkRstInt(i),
236  dataIn => gtpRxDataRaw(i),
237  dataOut => gtpRxData(i),
238  dataKOut => gtpRxDataK(i),
239  codeErr => gtpRxDecErrInt(i),
240  dispErr => gtpRxDispErrInt(i));
241 
242  -- Assign internal signals to outputs
243  gtpRxDecErr(i) <= gtpRxDecErrInt(i);
244  gtpRxDispErr(i) <= gtpRxDispErrInt(i);
245 
246  end generate DUAL_INST_LOOP;
247 
248  --------------------------------------------------------------------------------------------------
249  -- Tx Data Path
250  --------------------------------------------------------------------------------------------------
251  GtpTxPhaseAligner_1 : entity work.GtpTxPhaseAligner
252  generic map (
253  TPD_G => TPD_G)
254  port map (
255  gtpTxUsrClk2 => gtpTxUsrClk2,
256  gtpReset => gtpReset,
257  gtpPllLockDetect => gtpPllLockDetInt,
258  gtpTxEnPmaPhaseAlign => gtpTxEnPmaPhaseAlign,
259  gtpTxPmaSetPhase => gtpTxPmaSetPhase,
260  gtpTxAligned => gtpTxAligned);
261 
262  REFCLK_BUFG : BUFG
263  port map (
264  I => tmpRefClkOut,
265  O => gtpRefClkOut);
266 
267  gtpPllLockDet <= gtpPllLockDetInt;
268 
269  --------------------------------------------------------------------------------------------------
270  -- GTP Instance
271  --------------------------------------------------------------------------------------------------
272 
273 
274  ----------------------------- GTP_DUAL Instance --------------------------
275  UGtpDual : GTP_DUAL
276  generic map (
277 
278  --_______________________ Simulation-Only Attributes ___________________
279 
280  SIM_GTPRESET_SPEEDUP => 0,
281  SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2, -- x"0C8",
282 
283  --___________________________ Shared Attributes ________________________
284 
285  -------------------------- Tile and PLL Attributes ---------------------
286 
287  CLK25_DIVIDER => CLK25_DIVIDER, -- For 125 MHz clkin
288  CLKINDC_B => true,
289  OOB_CLK_DIVIDER => 6,
290  OVERSAMPLE_MODE => false,
291  PLL_DIVSEL_FB => PLL_DIVSEL_FB,
292  PLL_DIVSEL_REF => PLL_DIVSEL_REF, -- creates pll clock = 2.5 GHz w/ 125 Mhz clkin
293  PLL_TXDIVSEL_COMM_OUT => 1,
294  TX_SYNC_FILTERB => 1,
295 
296  --____________________ Transmit Interface Attributes ___________________
297 
298  ------------------- TX Buffering and Phase Alignment -------------------
299 
300  TX_BUFFER_USE_0 => false,
301  TX_XCLK_SEL_0 => "TXUSR",
302  TXRX_INVERT_0 => "00100",
303 
304  TX_BUFFER_USE_1 => false,
305  TX_XCLK_SEL_1 => "TXUSR",
306  TXRX_INVERT_1 => "00100",
307 
308  --------------------- TX Serial Line Rate settings ---------------------
309 
310  PLL_TXDIVSEL_OUT_0 => 1, -- Must be 1 when TX_BUFFER_USE = false
311 
312  PLL_TXDIVSEL_OUT_1 => 1,
313 
314  --------------------- TX Driver and OOB signalling --------------------
315 
316  TX_DIFF_BOOST_0 => true,
317 
318  TX_DIFF_BOOST_1 => true,
319 
320  ------------------ TX Pipe Control for PCI Express/SATA ---------------
321 
322  COM_BURST_VAL_0 => "1111",
323 
324  COM_BURST_VAL_1 => "1111",
325  --_______________________ Receive Interface Attributes ________________
326 
327  ------------ RX Driver,OOB signalling,Coupling and Eq,CDR -------------
328 
329  AC_CAP_DIS_0 => true,
330  OOBDETECT_THRESHOLD_0 => "001",
331  PMA_CDR_SCAN_0 => x"6c07640",
332  PMA_RX_CFG_0 => x"09f0089",
333  RCV_TERM_GND_0 => false,
334  RCV_TERM_MID_0 => false,
335  RCV_TERM_VTTRX_0 => false,
336  TERMINATION_IMP_0 => 50,
337 
338  AC_CAP_DIS_1 => true,
339  OOBDETECT_THRESHOLD_1 => "001",
340  PMA_CDR_SCAN_1 => x"6c07640",
341  PMA_RX_CFG_1 => x"09f0089",
342  RCV_TERM_GND_1 => false,
343  RCV_TERM_MID_1 => false,
344  RCV_TERM_VTTRX_1 => false,
345  TERMINATION_IMP_1 => 50,
346  TERMINATION_CTRL => "10100",
347  TERMINATION_OVRD => false,
348 
349  --------------------- RX Serial Line Rate Attributes ------------------
350 
351  PLL_RXDIVSEL_OUT_0 => 1,
352  PLL_SATA_0 => true,
353 
354  PLL_RXDIVSEL_OUT_1 => 1,
355  PLL_SATA_1 => true,
356 
357  ----------------------- PRBS Detection Attributes ---------------------
358 
359  PRBS_ERR_THRESHOLD_0 => x"00000001",
360 
361  PRBS_ERR_THRESHOLD_1 => x"00000001",
362 
363  ---------------- Comma Detection and Alignment Attributes -------------
364 
365  ALIGN_COMMA_WORD_0 => 2,
366  COMMA_10B_ENABLE_0 => "1111111111",
367  COMMA_DOUBLE_0 => false,
368  DEC_MCOMMA_DETECT_0 => false,
369  DEC_PCOMMA_DETECT_0 => false,
370  DEC_VALID_COMMA_ONLY_0 => false,
371  MCOMMA_10B_VALUE_0 => "1010000011",
372  MCOMMA_DETECT_0 => false,
373  PCOMMA_10B_VALUE_0 => "0101111100",
374  PCOMMA_DETECT_0 => false,
375  RX_SLIDE_MODE_0 => "PMA",
376 
377  ALIGN_COMMA_WORD_1 => 2,
378  COMMA_10B_ENABLE_1 => "1111111111",
379  COMMA_DOUBLE_1 => false,
380  DEC_MCOMMA_DETECT_1 => false,
381  DEC_PCOMMA_DETECT_1 => false,
382  DEC_VALID_COMMA_ONLY_1 => false,
383  MCOMMA_10B_VALUE_1 => "1010000011",
384  MCOMMA_DETECT_1 => false,
385  PCOMMA_10B_VALUE_1 => "0101111100",
386  PCOMMA_DETECT_1 => false,
387  RX_SLIDE_MODE_1 => "PMA",
388 
389  ------------------ RX Loss-of-sync State Machine Attributes -----------
390 
391  RX_LOSS_OF_SYNC_FSM_0 => false,
392  RX_LOS_INVALID_INCR_0 => 8,
393  RX_LOS_THRESHOLD_0 => 128,
394 
395  RX_LOSS_OF_SYNC_FSM_1 => false,
396  RX_LOS_INVALID_INCR_1 => 8,
397  RX_LOS_THRESHOLD_1 => 128,
398 
399  -------------- RX Elastic Buffer and Phase alignment Attributes -------
400 
401  RX_BUFFER_USE_0 => false,
402  RX_XCLK_SEL_0 => "RXUSR",
403 
404  RX_BUFFER_USE_1 => false,
405  RX_XCLK_SEL_1 => "RXUSR",
406 
407  ------------------------ Clock Correction Attributes ------------------
408 
409  CLK_CORRECT_USE_0 => false,
410  CLK_COR_ADJ_LEN_0 => 4,
411  CLK_COR_DET_LEN_0 => 4,
412  CLK_COR_INSERT_IDLE_FLAG_0 => false,
413  CLK_COR_KEEP_IDLE_0 => false,
414  CLK_COR_MAX_LAT_0 => 48,
415  CLK_COR_MIN_LAT_0 => 36,
416  CLK_COR_PRECEDENCE_0 => true,
417  CLK_COR_REPEAT_WAIT_0 => 0,
418  CLK_COR_SEQ_1_1_0 => "0110111100",
419  CLK_COR_SEQ_1_2_0 => "0100011100",
420  CLK_COR_SEQ_1_3_0 => "0100011100",
421  CLK_COR_SEQ_1_4_0 => "0100011100",
422  CLK_COR_SEQ_1_ENABLE_0 => "1111",
423  CLK_COR_SEQ_2_1_0 => "0000000000",
424  CLK_COR_SEQ_2_2_0 => "0000000000",
425  CLK_COR_SEQ_2_3_0 => "0000000000",
426  CLK_COR_SEQ_2_4_0 => "0000000000",
427  CLK_COR_SEQ_2_ENABLE_0 => "0000",
428  CLK_COR_SEQ_2_USE_0 => false,
429  RX_DECODE_SEQ_MATCH_0 => true,
430 
431  CLK_CORRECT_USE_1 => false,
432  CLK_COR_ADJ_LEN_1 => 4,
433  CLK_COR_DET_LEN_1 => 4,
434  CLK_COR_INSERT_IDLE_FLAG_1 => false,
435  CLK_COR_KEEP_IDLE_1 => false,
436  CLK_COR_MAX_LAT_1 => 48,
437  CLK_COR_MIN_LAT_1 => 36,
438  CLK_COR_PRECEDENCE_1 => true,
439  CLK_COR_REPEAT_WAIT_1 => 0,
440  CLK_COR_SEQ_1_1_1 => "1101111100",
441  CLK_COR_SEQ_1_2_1 => "1000111100",
442  CLK_COR_SEQ_1_3_1 => "1000111100",
443  CLK_COR_SEQ_1_4_1 => "1000111100",
444  CLK_COR_SEQ_1_ENABLE_1 => "1111",
445  CLK_COR_SEQ_2_1_1 => "0000000000",
446  CLK_COR_SEQ_2_2_1 => "0000000000",
447  CLK_COR_SEQ_2_3_1 => "0000000000",
448  CLK_COR_SEQ_2_4_1 => "0000000000",
449  CLK_COR_SEQ_2_ENABLE_1 => "0000",
450  CLK_COR_SEQ_2_USE_1 => false,
451  RX_DECODE_SEQ_MATCH_1 => true,
452 
453  ------------------------ Channel Bonding Attributes -------------------
454 
455  CHAN_BOND_1_MAX_SKEW_0 => 1,
456  CHAN_BOND_2_MAX_SKEW_0 => 1,
457  CHAN_BOND_LEVEL_0 => 0,
458  CHAN_BOND_MODE_0 => "OFF",
459  CHAN_BOND_SEQ_1_1_0 => "0000000000",
460  CHAN_BOND_SEQ_1_2_0 => "0000000000",
461  CHAN_BOND_SEQ_1_3_0 => "0000000000",
462  CHAN_BOND_SEQ_1_4_0 => "0000000000",
463  CHAN_BOND_SEQ_1_ENABLE_0 => "0000",
464  CHAN_BOND_SEQ_2_1_0 => "0000000000",
465  CHAN_BOND_SEQ_2_2_0 => "0000000000",
466  CHAN_BOND_SEQ_2_3_0 => "0000000000",
467  CHAN_BOND_SEQ_2_4_0 => "0000000000",
468  CHAN_BOND_SEQ_2_ENABLE_0 => "0000",
469  CHAN_BOND_SEQ_2_USE_0 => false,
470  CHAN_BOND_SEQ_LEN_0 => 1,
471  PCI_EXPRESS_MODE_0 => false,
472 
473  CHAN_BOND_1_MAX_SKEW_1 => 1,
474  CHAN_BOND_2_MAX_SKEW_1 => 1,
475  CHAN_BOND_LEVEL_1 => 0,
476  CHAN_BOND_MODE_1 => "OFF",
477  CHAN_BOND_SEQ_1_1_1 => "0000000000",
478  CHAN_BOND_SEQ_1_2_1 => "0000000000",
479  CHAN_BOND_SEQ_1_3_1 => "0000000000",
480  CHAN_BOND_SEQ_1_4_1 => "0000000000",
481  CHAN_BOND_SEQ_1_ENABLE_1 => "0000",
482  CHAN_BOND_SEQ_2_1_1 => "0000000000",
483  CHAN_BOND_SEQ_2_2_1 => "0000000000",
484  CHAN_BOND_SEQ_2_3_1 => "0000000000",
485  CHAN_BOND_SEQ_2_4_1 => "0000000000",
486  CHAN_BOND_SEQ_2_ENABLE_1 => "0000",
487  CHAN_BOND_SEQ_2_USE_1 => false,
488  CHAN_BOND_SEQ_LEN_1 => 1,
489  PCI_EXPRESS_MODE_1 => false,
490 
491  ------------------ RX Attributes for PCI Express/SATA ---------------
492 
493  RX_STATUS_FMT_0 => "PCIE",
494  SATA_BURST_VAL_0 => "100",
495  SATA_IDLE_VAL_0 => "100",
496  SATA_MAX_BURST_0 => 7,
497  SATA_MAX_INIT_0 => 22,
498  SATA_MAX_WAKE_0 => 7,
499  SATA_MIN_BURST_0 => 4,
500  SATA_MIN_INIT_0 => 12,
501  SATA_MIN_WAKE_0 => 4,
502  TRANS_TIME_FROM_P2_0 => x"0060",
503  TRANS_TIME_NON_P2_0 => x"0025",
504  TRANS_TIME_TO_P2_0 => x"0100",
505 
506  RX_STATUS_FMT_1 => "PCIE",
507  SATA_BURST_VAL_1 => "100",
508  SATA_IDLE_VAL_1 => "100",
509  SATA_MAX_BURST_1 => 7,
510  SATA_MAX_INIT_1 => 22,
511  SATA_MAX_WAKE_1 => 7,
512  SATA_MIN_BURST_1 => 4,
513  SATA_MIN_INIT_1 => 12,
514  SATA_MIN_WAKE_1 => 4,
515  TRANS_TIME_FROM_P2_1 => x"0060",
516  TRANS_TIME_NON_P2_1 => x"0025",
517  TRANS_TIME_TO_P2_1 => x"0100"
518 
519  )
520  port map (
521 
522  ------------------------ Loopback and Powerdown Ports ----------------------
523  LOOPBACK0(0) => '0',
524  LOOPBACK0(1) => gtpLoopback(0),
525  LOOPBACK0(2) => '0',
526  LOOPBACK1(0) => '0',
527  LOOPBACK1(1) => gtpLoopback(1),
528  LOOPBACK1(2) => '0',
529  RXPOWERDOWN0 => (others => '0'),
530  RXPOWERDOWN1 => (others => '0'),
531  TXPOWERDOWN0 => (others => '0'),
532  TXPOWERDOWN1 => (others => '0'),
533  ----------------------- Receive Ports - 8b10b Decoder ----------------------
534  RXCHARISCOMMA0 => open,
535  RXCHARISCOMMA1 => open,
536  RXCHARISK0(0) => gtpRxDataRaw(0)(8),
537  RXCHARISK0(1) => gtpRxDataRaw(0)(18),
538  RXCHARISK1(0) => gtpRxDataRaw(1)(8),
539  RXCHARISK1(1) => gtpRxDataRaw(1)(18),
540  RXDEC8B10BUSE0 => '0',
541  RXDEC8B10BUSE1 => '0',
542  RXDISPERR0(0) => gtpRxDataRaw(0)(9),
543  RXDISPERR0(1) => gtpRxDataRaw(0)(19),
544  RXDISPERR1(0) => gtpRxDataRaw(1)(9),
545  RXDISPERR1(1) => gtpRxDataRaw(1)(19),
546  RXNOTINTABLE0 => open,
547  RXNOTINTABLE1 => open,
548  RXRUNDISP0 => open,
549  RXRUNDISP1 => open,
550  ------------------- Receive Ports - Channel Bonding Ports ------------------
551  RXCHANBONDSEQ0 => open,
552  RXCHANBONDSEQ1 => open,
553  RXCHBONDI0 => (others => '0'),
554  RXCHBONDI1 => (others => '0'),
555  RXCHBONDO0 => open,
556  RXCHBONDO1 => open,
557  RXENCHANSYNC0 => '0',
558  RXENCHANSYNC1 => '0',
559  ------------------- Receive Ports - Clock Correction Ports -----------------
560  RXCLKCORCNT0 => open,
561  RXCLKCORCNT1 => open,
562  --------------- Receive Ports - Comma Detection and Alignment --------------
563  RXBYTEISALIGNED0 => open,
564  RXBYTEISALIGNED1 => open,
565  RXBYTEREALIGN0 => open,
566  RXBYTEREALIGN1 => open,
567  RXCOMMADET0 => open,
568  RXCOMMADET1 => open,
569  RXCOMMADETUSE0 => '0',
570  RXCOMMADETUSE1 => '0',
571  RXENMCOMMAALIGN0 => '0',
572  RXENMCOMMAALIGN1 => '0',
573  RXENPCOMMAALIGN0 => '0',
574  RXENPCOMMAALIGN1 => '0',
575  RXSLIDE0 => gtpRxSlide(0),
576  RXSLIDE1 => gtpRxSlide(1),
577  ----------------------- Receive Ports - PRBS Detection ---------------------
578  PRBSCNTRESET0 => '0',
579  PRBSCNTRESET1 => '0',
580  RXENPRBSTST0 => (others => '0'),
581  RXENPRBSTST1 => (others => '0'),
582  RXPRBSERR0 => open,
583  RXPRBSERR1 => open,
584  ------------------- Receive Ports - RX Data Path interface -----------------
585  RXDATA0(7 downto 0) => gtpRxDataRaw(0)(7 downto 0),
586  RXDATA0(15 downto 8) => gtpRxDataRaw(0)(17 downto 10),
587  RXDATA1(7 downto 0) => gtpRxDataRaw(1)(7 downto 0),
588  RXDATA1(15 downto 8) => gtpRxDataRaw(1)(17 downto 10),
589  RXDATAWIDTH0 => '1',
590  RXDATAWIDTH1 => '1',
591  RXRECCLK0 => gtpRxRecClk(0),
592  RXRECCLK1 => gtpRxRecClk(1),
593  RXRESET0 => gtpRxReset(0),
594  RXRESET1 => gtpRxReset(1),
595  RXUSRCLK0 => gtpRxUsrClkInt(0),
596  RXUSRCLK1 => gtpRxUsrClkInt(1),
597  RXUSRCLK20 => gtpRxUsrClk2Int(0),
598  RXUSRCLK21 => gtpRxUsrClk2Int(1),
599  ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
600  RXCDRRESET0 => gtpRxCdrResetFinal(0),
601  RXCDRRESET1 => gtpRxCdrResetFinal(1),
602  RXELECIDLE0 => gtpRxElecIdle(0),
603  RXELECIDLE1 => gtpRxElecIdle(1),
604  RXELECIDLERESET0 => gtpRxElecIdleRst(0),
605  RXELECIDLERESET1 => gtpRxElecIdleRst(1),
606  RXENEQB0 => '0',
607  RXENEQB1 => '0',
608  RXEQMIX0 => (others => '0'),
609  RXEQMIX1 => (others => '0'),
610  RXEQPOLE0 => (others => '0'),
611  RXEQPOLE1 => (others => '0'),
612  RXN0 => gtpRxN(0),
613  RXN1 => gtpRxN(1),
614  RXP0 => gtpRxP(0),
615  RXP1 => gtpRxP(1),
616  -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
617  RXBUFRESET0 => '0',
618  RXBUFRESET1 => '0',
619  RXBUFSTATUS0 => open,
620  RXBUFSTATUS1 => open,
621  RXCHANISALIGNED0 => open,
622  RXCHANISALIGNED1 => open,
623  RXCHANREALIGN0 => open,
624  RXCHANREALIGN1 => open,
625  RXPMASETPHASE0 => '0',
626  RXPMASETPHASE1 => '0',
627  RXSTATUS0 => open,
628  RXSTATUS1 => open,
629  --------------- Receive Ports - RX Loss-of-sync State Machine --------------
630  RXLOSSOFSYNC0 => open,
631  RXLOSSOFSYNC1 => open,
632  ---------------------- Receive Ports - RX Oversampling ---------------------
633  RXENSAMPLEALIGN0 => '0',
634  RXENSAMPLEALIGN1 => '0',
635  RXOVERSAMPLEERR0 => open,
636  RXOVERSAMPLEERR1 => open,
637  -------------- Receive Ports - RX Pipe Control for PCI Express -------------
638  PHYSTATUS0 => open,
639  PHYSTATUS1 => open,
640  RXVALID0 => open,
641  RXVALID1 => open,
642  ----------------- Receive Ports - RX Polarity Control Ports ----------------
643  RXPOLARITY0 => gtpRxPolarity(0),
644  RXPOLARITY1 => gtpRxPolarity(1),
645  ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
646  DADDR => (others => '0'),
647  DCLK => '0',
648  DEN => '0',
649  DI => (others => '0'),
650  DO => open,
651  DRDY => open,
652  DWE => '0',
653  --------------------- Shared Ports - Tile and PLL Ports --------------------
654  CLKIN => gtpClkIn,
655  GTPRESET => gtpReset,
656  GTPTEST => (others => '0'),
657  INTDATAWIDTH => '1',
658  PLLLKDET => gtpPllLockDetInt,
659  PLLLKDETEN => '1',
660  PLLPOWERDOWN => '0',
661  REFCLKOUT => tmpRefClkOut,
662  REFCLKPWRDNB => '1',
663  RESETDONE0 => gtpResetDone(0),
664  RESETDONE1 => gtpResetDone(1),
665  RXENELECIDLERESETB => '1',
666  TXENPMAPHASEALIGN => gtpTxEnPmaPhaseAlign,
667  TXPMASETPHASE => gtpTxPmaSetPhase,
668  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
669  TXBYPASS8B10B0 => (others => '0'),
670  TXBYPASS8B10B1 => (others => '0'),
671  TXCHARDISPMODE0 => (others => '0'),
672  TXCHARDISPMODE1 => (others => '0'),
673  TXCHARDISPVAL0 => (others => '0'),
674  TXCHARDISPVAL1 => (others => '0'),
675  TXCHARISK0 => gtpTxDataK(0),
676  TXCHARISK1 => gtpTxDataK(1),
677  TXENC8B10BUSE0 => '1',
678  TXENC8B10BUSE1 => '1',
679  TXKERR0 => open, --txKerr,
680  TXKERR1 => open,
681  TXRUNDISP0 => open,
682  TXRUNDISP1 => open,
683  ------------- Transmit Ports - TX Buffering and Phase Alignment ------------
684  TXBUFSTATUS0 => open,
685  TXBUFSTATUS1 => open,
686  ------------------ Transmit Ports - TX Data Path interface -----------------
687  TXDATA0 => gtpTxData(0),
688  TXDATA1 => gtpTxData(1),
689  TXDATAWIDTH0 => '1',
690  TXDATAWIDTH1 => '1',
691  TXOUTCLK0 => open,
692  TXOUTCLK1 => open,
693  TXRESET0 => gtpTxReset(0),
694  TXRESET1 => gtpTxReset(1),
695  TXUSRCLK0 => gtpTxUsrClk,
696  TXUSRCLK1 => gtpTxUsrClk,
697  TXUSRCLK20 => gtpTxUsrClk2,
698  TXUSRCLK21 => gtpTxUsrClk2,
699  --------------- Transmit Ports - TX Driver and OOB signalling --------------
700  TXBUFDIFFCTRL0 => "100", -- 800mV
701  TXBUFDIFFCTRL1 => "100",
702  TXDIFFCTRL0 => "100",
703  TXDIFFCTRL1 => "100",
704  TXINHIBIT0 => '0',
705  TXINHIBIT1 => '0',
706  TXN0 => gtpTxN(0),
707  TXN1 => gtpTxN(1),
708  TXP0 => gtpTxP(0),
709  TXP1 => gtpTxP(1),
710  TXPREEMPHASIS0 => "011", -- 4.5%
711  TXPREEMPHASIS1 => "011",
712  --------------------- Transmit Ports - TX PRBS Generator -------------------
713  TXENPRBSTST0 => (others => '0'),
714  TXENPRBSTST1 => (others => '0'),
715  -------------------- Transmit Ports - TX Polarity Control ------------------
716  TXPOLARITY0 => '0',
717  TXPOLARITY1 => '0',
718  ----------------- Transmit Ports - TX Ports for PCI Express ----------------
719  TXDETECTRX0 => '0',
720  TXDETECTRX1 => '0',
721  TXELECIDLE0 => '0',
722  TXELECIDLE1 => '0',
723  --------------------- Transmit Ports - TX Ports for SATA -------------------
724  TXCOMSTART0 => '0',
725  TXCOMSTART1 => '0',
726  TXCOMTYPE0 => '0',
727  TXCOMTYPE1 => '0'
728  );
729 
730 
731 end rtl;
GtpDualFixedLatCore.gtpRxReset
in gtpRxResetslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:58
GtpDualFixedLatCore.gtpLoopback
in gtpLoopbackslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:55
Decoder8b10b.NUM_BYTES_G
NUM_BYTES_Gpositive := 2
Definition: Decoder8b10b.vhd:29
Decoder8b10b.RST_POLARITY_G
RST_POLARITY_Gsl := '1'
Definition: Decoder8b10b.vhd:30
GtpDualFixedLatCore.gtpRxPolarity
in gtpRxPolarityslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:73
GtpDualFixedLatCore.SIM_PLL_PERDIV2
SIM_PLL_PERDIV2bit_vector := X"0C8"
Definition: GtpDualFixedLatCore.vhd:31
GtpDualFixedLatCore.gtpRxAligned
out gtpRxAlignedslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:74
RstSync.syncRst
out syncRstsl
Definition: RstSync.vhd:36
RstSync.IN_POLARITY_G
IN_POLARITY_Gsl := '1'
Definition: RstSync.vhd:28
GtpDualFixedLatCore.gtpRxUsrClk2
out gtpRxUsrClk2slv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:65
GtpRxCommaAligner.gtpRxSlide
out gtpRxSlidestd_logic
Definition: GtpRxCommaAligner.vhd:36
GtpDualFixedLatCore.gtpTxData
in gtpTxDataslv16Array( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:86
Decoder8b10b.TPD_G
TPD_Gtime := 1 ns
Definition: Decoder8b10b.vhd:28
Decoder8b10b.dataOut
out dataOutslv( NUM_BYTES_G* 8- 1 downto 0)
Definition: Decoder8b10b.vhd:38
GtpDualFixedLatCore.gtpRxP
in gtpRxPslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:47
Decoder8b10b.codeErr
out codeErrslv( NUM_BYTES_G- 1 downto 0)
Definition: Decoder8b10b.vhd:41
GtpDualFixedLatCore.gtpResetDone
out gtpResetDoneslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:53
GtpRxCommaAligner.gtpRxData
in gtpRxDatastd_logic_vector( 19 downto 0)
Definition: GtpRxCommaAligner.vhd:32
Gtp16FixedLatCore.UNISIM
_library_ UNISIMUNISIM
Definition: Gtp16FixedLatCore.vhd:20
Decoder8b10b.dispErr
out dispErrslv( NUM_BYTES_G- 1 downto 0)
Definition: Decoder8b10b.vhd:42
GtpTxPhaseAligner.gtpTxUsrClk2
in gtpTxUsrClk2std_logic
Definition: GtpTxPhaseAligner.vhd:30
GtpTxPhaseAligner.gtpTxEnPmaPhaseAlign
out gtpTxEnPmaPhaseAlignstd_logic
Definition: GtpTxPhaseAligner.vhd:33
RstSync.asyncRst
in asyncRstsl
Definition: RstSync.vhd:35
GtpRxCommaAligner.aligned
out alignedstd_logic
Definition: GtpRxCommaAligner.vhd:38
RstSync.clk
in clksl
Definition: RstSync.vhd:34
RstSync.OUT_POLARITY_G
OUT_POLARITY_Gsl := '1'
Definition: RstSync.vhd:29
GtpDualFixedLatCore.gtpTxN
out gtpTxNslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:48
GtpRxCommaAligner.gtpRxUsrClk2Sel
out gtpRxUsrClk2Selstd_logic
Definition: GtpRxCommaAligner.vhd:35
GtpTxPhaseAligner.gtpTxPmaSetPhase
out gtpTxPmaSetPhasestd_logic
Definition: GtpTxPhaseAligner.vhd:34
GtpRxCommaAligner.dispErr
in dispErrstd_logic_vector( 1 downto 0)
Definition: GtpRxCommaAligner.vhd:34
RstSync.RELEASE_DELAY_G
RELEASE_DELAY_Ginteger range 3 to positive'high:= 3
Definition: RstSync.vhd:31
GtpDualFixedLatCore.gtpRxDataK
out gtpRxDataKslv2Array( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:70
GtpTxPhaseAligner.gtpPllLockDetect
in gtpPllLockDetectstd_logic
Definition: GtpTxPhaseAligner.vhd:32
GtpRxCommaAligner.gtpRxCdrReset
out gtpRxCdrResetstd_logic
Definition: GtpRxCommaAligner.vhd:37
GtpDualFixedLatCore.gtpRxElecIdle
out gtpRxElecIdleslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:60
GtpDualFixedLatCore.gtpRxN
in gtpRxNslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:46
RstSync.TPD_G
TPD_Gtime := 1 ns
Definition: RstSync.vhd:27
GtpTxPhaseAligner.gtpTxAligned
out gtpTxAlignedstd_logic
Definition: GtpTxPhaseAligner.vhd:35
GtpDualFixedLatCore.gtpRxDecErr
out gtpRxDecErrslv2Array( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:71
GtpDualFixedLatCore.gtpTxDataK
in gtpTxDataKslv2Array( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:88
GtpDualFixedLatCore.gtpRxUsrClk
out gtpRxUsrClkslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:64
Decoder8b10b.dataIn
in dataInslv( NUM_BYTES_G* 10- 1 downto 0)
Definition: Decoder8b10b.vhd:37
Decoder8b10b.dataKOut
out dataKOutslv( NUM_BYTES_G- 1 downto 0)
Definition: Decoder8b10b.vhd:39
GtpDualFixedLatCore.gtpRxData
out gtpRxDataslv16Array( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:69
Decoder8b10b.rst
in rstsl :=not RST_POLARITY_G
Definition: Decoder8b10b.vhd:35
GtpDualFixedLatCore.gtpRxCdrReset
in gtpRxCdrResetslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:59
GtpDualFixedLatCore.gtpRxDispErr
out gtpRxDispErrslv2Array( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:72
GtpRxCommaAligner.gtpRxUsrClk2Rst
in gtpRxUsrClk2Rststd_logic
Definition: GtpRxCommaAligner.vhd:31
GtpDualFixedLatCore.gtpRxElecIdleRst
in gtpRxElecIdleRstslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:61
GtpDualFixedLatCore.gtpTxP
out gtpTxPslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:49
GtpDualFixedLatCore.gtpRxUsrClkRst
out gtpRxUsrClkRstslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:66
GtpRxCommaAligner.codeErr
in codeErrstd_logic_vector( 1 downto 0)
Definition: GtpRxCommaAligner.vhd:33
Decoder8b10b.RST_ASYNC_G
RST_ASYNC_Gboolean := false
Definition: Decoder8b10b.vhd:31
GtpRxCommaAligner.gtpRxUsrClk2
in gtpRxUsrClk2std_logic
Definition: GtpRxCommaAligner.vhd:30
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
GtpDualFixedLatCore.gtpTxReset
in gtpTxResetslv( 1 downto 0)
Definition: GtpDualFixedLatCore.vhd:77