SURF  1.0
Gtp16FixedLatCore.vhd
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1 -------------------------------------------------------------------------------
2 -- File : Pgp2Gtp16FixedLatCore.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2012-11-28
5 -- Last update: 2013-08-02
6 -------------------------------------------------------------------------------
7 -- Description: Pgp2 Gtp Low Latency Core
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 library UNISIM;
21 use UNISIM.VCOMPONENTS.all;
22 use work.StdRtlPkg.all;
23 
24 --! @see entity
25  --! @ingroup xilinx_Virtex5_gtp
26 entity Gtp16FixedLatCore is
27  generic (
28  TPD_G : time := 1 ns;
29 
30  -- GTP Parameters
31  SIM_PLL_PERDIV2 : bit_vector := X"0C8";
32  CLK25_DIVIDER : integer := 5;
33  PLL_DIVSEL_FB : integer := 2;
34  PLL_DIVSEL_REF : integer := 1;
35 
36  -- Recovered clock parameters
37  REC_CLK_PERIOD : real := 4.000;
38  REC_PLL_MULT : integer := 4;
39  REC_PLL_DIV : integer := 1
40  );
41  port (
42 
43  -- GTP Signals
44  gtpClkIn : in sl; -- GTP Reference Clock In
45  gtpRefClkOut : out sl; -- GTP Reference Clock Output
46  gtpRxN : in sl; -- GTP Serial Receive Negative
47  gtpRxP : in sl; -- GTP Serial Receive Positive
48  gtpTxN : out sl; -- GTP Serial Transmit Negative
49  gtpTxP : out sl; -- GTP Serial Transmit Positive
50 
51  -- Shared
52  gtpReset : in sl;
53  gtpResetDone : out sl;
54  gtpPllLockDet : out sl;
55  gtpLoopback : in sl;
56 
57  -- Rx Resets
58  gtpRxReset : in sl;
59  gtpRxCdrReset : in sl;
60  gtpRxElecIdle : out sl;
61  gtpRxElecIdleRst : in sl;
62 
63  -- Rx Clocks
64  gtpRxUsrClk : out sl; -- 1 byte clock (recovered)
65  gtpRxUsrClk2 : out sl; -- 2 byte clock (recovered)
66  gtpRxUsrClkRst : out sl; -- Reset for 2 byte clock
67 
68  -- Rx Data
69  gtpRxData : out slv(15 downto 0);
70  gtpRxDataK : out slv(1 downto 0);
71  gtpRxDecErr : out slv(1 downto 0);
72  gtpRxDispErr : out slv(1 downto 0);
73  gtpRxPolarity : in sl;
74  gtpRxAligned : out sl;
75 
76  -- Tx Resets
77  gtpTxReset : in sl;
78 
79  -- Tx Clocks
80  gtpTxUsrClk : in sl;
81  gtpTxUsrClk2 : in sl;
82 
83  gtpTxAligned : out sl;
84 
85  -- Tx Data
86  gtpTxData : in slv(15 downto 0);
87  gtpTxDataK : in slv(1 downto 0)
88  );
89 
90 end Gtp16FixedLatCore;
91 
92 architecture rtl of Gtp16FixedLatCore is
93 
94  signal gtpPllLockDetInt : sl;
95  signal tmpRefClkOut : sl;
96 
97  --------------------------------------------------------------------------------------------------
98  -- Rx Signals
99  --------------------------------------------------------------------------------------------------
100  -- Clocking
101  signal gtpRxRecClk : sl; -- Raw rxrecclk from GTP, not square, needs DCM or PLL
102  signal gtpRxRecClkBufG : sl;
103  signal rxRecClkPllOut0 : sl; -- 1 byte clock
104  signal rxRecClkPllOut1 : sl; -- 2 byte clock
105  signal rxRecClkPllOut2 : sl; -- 2 byte clock (180 deg phase shift)
106  signal rxRecClkPllFbIn : sl;
107  signal rxRecClkPllFbOut : sl;
108  signal rxRecClkPllLocked : sl;
109  signal rxUsrClk2Sel : sl; -- Selects which 2 byte clock is used
110  signal gtpRxUsrClkInt : sl;
111  signal gtpRxUsrClk2Int : sl;
112  signal gtpRxUsrClkRstInt : sl;
113 
114  -- Rx Data
115  signal gtpRxDataRaw : slv(19 downto 0);
116  signal gtpRxDecErrInt : slv(1 downto 0);
117  signal gtpRxDispErrInt : slv(1 downto 0);
118 
119  -- Rx Phase Alignment
120  signal gtpRxSlide : sl;
121 
122  -- Tx Phase Alignment
123  signal gtpTxEnPmaPhaseAlign : sl;
124  signal gtpTxPmaSetPhase : sl;
125 
126  -- Resets
127  signal gtpRxCdrResetFinal : sl;
128  signal rxCommaAlignReset : sl;
129 
130 begin
131 
132  --------------------------------------------------------------------------------------------------
133  -- Rx Data Path
134  --------------------------------------------------------------------------------------------------
135  RX_REC_CLK_BUFG : BUFG
136  port map (
137  O => gtpRxRecClkBufG, -- Feeds pll clkin
138  I => gtpRxRecClk); -- From GTP RXRECCLK
139 
140  RX_REC_CLK_PLL : PLL_BASE
141  generic map(
142  BANDWIDTH => "OPTIMIZED",
143  CLKIN_PERIOD => REC_CLK_PERIOD,
144  CLKOUT0_DIVIDE => REC_PLL_MULT,
145  CLKOUT1_DIVIDE => REC_PLL_MULT * 2 ,
146  CLKOUT2_DIVIDE => REC_PLL_MULT * 2 ,
147  CLKOUT0_PHASE => 0.000,
148  CLKOUT1_PHASE => 0.000,
149  CLKOUT2_PHASE => 180.000,
150  CLKOUT0_DUTY_CYCLE => 0.500,
151  CLKOUT1_DUTY_CYCLE => 0.500,
152  CLKOUT2_DUTY_CYCLE => 0.500,
153  COMPENSATION => "SYSTEM_SYNCHRONOUS",
154  DIVCLK_DIVIDE => REC_PLL_DIV,
155  CLKFBOUT_MULT => REC_PLL_MULT,
156  CLKFBOUT_PHASE => 0.0,
157  REF_JITTER => 0.005000)
158  port map (
159  CLKFBIN => rxRecClkPllFbIn,
160  CLKIN => gtpRxRecClkBufG,
161  RST => '0',
162  CLKFBOUT => rxRecClkPllFbOut,
163  CLKOUT0 => rxRecClkPllOut0,
164  CLKOUT1 => rxRecClkPllOut1,
165  CLKOUT2 => rxRecClkPllOut2,
166  CLKOUT3 => open,
167  CLKOUT4 => open,
168  CLKOUT5 => open,
169  LOCKED => rxRecClkPllLocked);
170 
171  -- Feedback for PLL
172  RX_REC_CLK_PLL_FB_BUFG : BUFG
173  port map (
174  O => rxRecClkPllFbIn,
175  I => rxRecClkPllFbOut);
176 
177  -- Buffer pll outputs
178  RX_USR_CLK_BUFG : BUFG
179  port map (
180  I => rxRecClkPllOut0,
181  O => gtpRxUsrClkInt);
182 
183  RX_USR_CLK2_BUFMUX : BUFGMUX_CTRL
184  port map (
185  I1 => rxRecClkPllOut1,
186  I0 => rxRecClkPllOut2,
187  S => rxUsrClk2Sel,
188  O => gtpRxUsrClk2Int);
189 
190  RstSync_1 : entity work.RstSync
191  generic map (
192  TPD_G => TPD_G,
193  IN_POLARITY_G => '0',
194  OUT_POLARITY_G => '1',
195  RELEASE_DELAY_G => 3)
196  port map (
197  clk => gtpRxUsrClk2Int,
198  asyncRst => rxRecClkPllLocked,
199  syncRst => gtpRxUsrClkRstInt);
200 
201  -- Output recovered clocks for external use
202  gtpRxUsrClk2 <= gtpRxUsrClk2Int;
203  gtpRxUsrClk <= gtpRxUsrClkInt;
204  gtpRxUsrClkRst <= gtpRxUsrClkRstInt;
205 
206  -- Comma aligner and RxRst modules both drive CDR Reset
207  gtpRxCdrResetFinal <= gtpRxCdrReset or rxCommaAlignReset;
208 
209  -- Manual comma aligner
210  GtpRxCommaAligner_1 : entity work.GtpRxCommaAligner
211  generic map (
212  TPD_G => TPD_G)
213  port map (
214  gtpRxUsrClk2 => gtpRxUsrClk2Int,
215  gtpRxUsrClk2Rst => gtpRxUsrClkRstInt,
216  gtpRxData => gtpRxDataRaw,
217  codeErr => gtpRxDecErrInt,
218  dispErr => gtpRxDispErrInt,
219  gtpRxUsrClk2Sel => rxUsrClk2Sel,
220  gtpRxSlide => gtpRxSlide,
221  gtpRxCdrReset => rxCommaAlignReset,
222  aligned => gtpRxAligned);
223 
224  Decoder8b10b_1 : entity work.Decoder8b10b
225  generic map (
226  TPD_G => TPD_G,
227  NUM_BYTES_G => 2,
228  RST_POLARITY_G => '1',
229  RST_ASYNC_G => true)
230  port map (
231  clk => gtpRxUsrClk2Int,
232  rst => gtpRxUsrClkRstInt,
233  dataIn => gtpRxDataRaw,
234  dataOut => gtpRxData,
235  dataKOut => gtpRxDataK,
236  codeErr => gtpRxDecErrInt,
237  dispErr => gtpRxDispErrInt);
238 
239  -- Assign internal signals to outputs
240  gtpRxDecErr <= gtpRxDecErrInt;
241  gtpRxDispErr <= gtpRxDispErrInt;
242 
243 
244  --------------------------------------------------------------------------------------------------
245  -- Tx Data Path
246  --------------------------------------------------------------------------------------------------
247  GtpTxPhaseAligner_1 : entity work.GtpTxPhaseAligner
248  generic map (
249  TPD_G => TPD_G)
250  port map (
251  gtpTxUsrClk2 => gtpTxUsrClk2,
252  gtpReset => gtpReset,
253  gtpPllLockDetect => gtpPllLockDetInt,
254  gtpTxEnPmaPhaseAlign => gtpTxEnPmaPhaseAlign,
255  gtpTxPmaSetPhase => gtpTxPmaSetPhase,
256  gtpTxAligned => gtpTxAligned);
257 
258  REFCLK_BUFG : BUFG
259  port map (
260  I => tmpRefClkOut,
261  O => gtpRefClkOut);
262 
263  gtpPllLockDet <= gtpPllLockDetInt;
264 
265  --------------------------------------------------------------------------------------------------
266  -- GTP Instance
267  --------------------------------------------------------------------------------------------------
268 
269 
270  ----------------------------- GTP_DUAL Instance --------------------------
271  UGtpDual : GTP_DUAL
272  generic map (
273 
274  --_______________________ Simulation-Only Attributes ___________________
275 
276  SIM_GTPRESET_SPEEDUP => 0,
277  SIM_PLL_PERDIV2 => SIM_PLL_PERDIV2, -- x"0C8",
278 
279  --___________________________ Shared Attributes ________________________
280 
281  -------------------------- Tile and PLL Attributes ---------------------
282 
283  CLK25_DIVIDER => CLK25_DIVIDER, -- For 125 MHz clkin
284  CLKINDC_B => true,
285  OOB_CLK_DIVIDER => 6,
286  OVERSAMPLE_MODE => false,
287  PLL_DIVSEL_FB => PLL_DIVSEL_FB,
288  PLL_DIVSEL_REF => PLL_DIVSEL_REF, -- creates pll clock = 2.5 GHz w/ 125 Mhz clkin
289  PLL_TXDIVSEL_COMM_OUT => 1,
290  TX_SYNC_FILTERB => 1,
291 
292  --____________________ Transmit Interface Attributes ___________________
293 
294  ------------------- TX Buffering and Phase Alignment -------------------
295 
296  TX_BUFFER_USE_0 => false,
297  TX_XCLK_SEL_0 => "TXUSR",
298  TXRX_INVERT_0 => "00100",
299 
300  TX_BUFFER_USE_1 => false,
301  TX_XCLK_SEL_1 => "TXUSR",
302  TXRX_INVERT_1 => "00100",
303 
304  --------------------- TX Serial Line Rate settings ---------------------
305 
306  PLL_TXDIVSEL_OUT_0 => 1, -- Must be 1 when TX_BUFFER_USE = false
307 
308  PLL_TXDIVSEL_OUT_1 => 1,
309 
310  --------------------- TX Driver and OOB signalling --------------------
311 
312  TX_DIFF_BOOST_0 => true,
313 
314  TX_DIFF_BOOST_1 => true,
315 
316  ------------------ TX Pipe Control for PCI Express/SATA ---------------
317 
318  COM_BURST_VAL_0 => "1111",
319 
320  COM_BURST_VAL_1 => "1111",
321  --_______________________ Receive Interface Attributes ________________
322 
323  ------------ RX Driver,OOB signalling,Coupling and Eq,CDR -------------
324 
325  AC_CAP_DIS_0 => true,
326  OOBDETECT_THRESHOLD_0 => "001",
327  PMA_CDR_SCAN_0 => x"6c07640",
328  PMA_RX_CFG_0 => x"09f0089",
329  RCV_TERM_GND_0 => false,
330  RCV_TERM_MID_0 => false,
331  RCV_TERM_VTTRX_0 => false,
332  TERMINATION_IMP_0 => 50,
333 
334  AC_CAP_DIS_1 => true,
335  OOBDETECT_THRESHOLD_1 => "001",
336  PMA_CDR_SCAN_1 => x"6c07640",
337  PMA_RX_CFG_1 => x"09f0089",
338  RCV_TERM_GND_1 => false,
339  RCV_TERM_MID_1 => false,
340  RCV_TERM_VTTRX_1 => false,
341  TERMINATION_IMP_1 => 50,
342  TERMINATION_CTRL => "10100",
343  TERMINATION_OVRD => false,
344 
345  --------------------- RX Serial Line Rate Attributes ------------------
346 
347  PLL_RXDIVSEL_OUT_0 => 1,
348  PLL_SATA_0 => true,
349 
350  PLL_RXDIVSEL_OUT_1 => 1,
351  PLL_SATA_1 => true,
352 
353  ----------------------- PRBS Detection Attributes ---------------------
354 
355  PRBS_ERR_THRESHOLD_0 => x"00000001",
356 
357  PRBS_ERR_THRESHOLD_1 => x"00000001",
358 
359  ---------------- Comma Detection and Alignment Attributes -------------
360 
361  ALIGN_COMMA_WORD_0 => 2,
362  COMMA_10B_ENABLE_0 => "1111111111",
363  COMMA_DOUBLE_0 => false,
364  DEC_MCOMMA_DETECT_0 => false,
365  DEC_PCOMMA_DETECT_0 => false,
366  DEC_VALID_COMMA_ONLY_0 => false,
367  MCOMMA_10B_VALUE_0 => "1010000011",
368  MCOMMA_DETECT_0 => false,
369  PCOMMA_10B_VALUE_0 => "0101111100",
370  PCOMMA_DETECT_0 => false,
371  RX_SLIDE_MODE_0 => "PMA",
372 
373  ALIGN_COMMA_WORD_1 => 2,
374  COMMA_10B_ENABLE_1 => "1111111111",
375  COMMA_DOUBLE_1 => false,
376  DEC_MCOMMA_DETECT_1 => false,
377  DEC_PCOMMA_DETECT_1 => false,
378  DEC_VALID_COMMA_ONLY_1 => false,
379  MCOMMA_10B_VALUE_1 => "1010000011",
380  MCOMMA_DETECT_1 => false,
381  PCOMMA_10B_VALUE_1 => "0101111100",
382  PCOMMA_DETECT_1 => false,
383  RX_SLIDE_MODE_1 => "PMA",
384 
385  ------------------ RX Loss-of-sync State Machine Attributes -----------
386 
387  RX_LOSS_OF_SYNC_FSM_0 => false,
388  RX_LOS_INVALID_INCR_0 => 8,
389  RX_LOS_THRESHOLD_0 => 128,
390 
391  RX_LOSS_OF_SYNC_FSM_1 => false,
392  RX_LOS_INVALID_INCR_1 => 8,
393  RX_LOS_THRESHOLD_1 => 128,
394 
395  -------------- RX Elastic Buffer and Phase alignment Attributes -------
396 
397  RX_BUFFER_USE_0 => false,
398  RX_XCLK_SEL_0 => "RXUSR",
399 
400  RX_BUFFER_USE_1 => false,
401  RX_XCLK_SEL_1 => "RXUSR",
402 
403  ------------------------ Clock Correction Attributes ------------------
404 
405  CLK_CORRECT_USE_0 => false,
406  CLK_COR_ADJ_LEN_0 => 4,
407  CLK_COR_DET_LEN_0 => 4,
408  CLK_COR_INSERT_IDLE_FLAG_0 => false,
409  CLK_COR_KEEP_IDLE_0 => false,
410  CLK_COR_MAX_LAT_0 => 48,
411  CLK_COR_MIN_LAT_0 => 36,
412  CLK_COR_PRECEDENCE_0 => true,
413  CLK_COR_REPEAT_WAIT_0 => 0,
414  CLK_COR_SEQ_1_1_0 => "0110111100",
415  CLK_COR_SEQ_1_2_0 => "0100011100",
416  CLK_COR_SEQ_1_3_0 => "0100011100",
417  CLK_COR_SEQ_1_4_0 => "0100011100",
418  CLK_COR_SEQ_1_ENABLE_0 => "1111",
419  CLK_COR_SEQ_2_1_0 => "0000000000",
420  CLK_COR_SEQ_2_2_0 => "0000000000",
421  CLK_COR_SEQ_2_3_0 => "0000000000",
422  CLK_COR_SEQ_2_4_0 => "0000000000",
423  CLK_COR_SEQ_2_ENABLE_0 => "0000",
424  CLK_COR_SEQ_2_USE_0 => false,
425  RX_DECODE_SEQ_MATCH_0 => true,
426 
427  CLK_CORRECT_USE_1 => false,
428  CLK_COR_ADJ_LEN_1 => 4,
429  CLK_COR_DET_LEN_1 => 4,
430  CLK_COR_INSERT_IDLE_FLAG_1 => false,
431  CLK_COR_KEEP_IDLE_1 => false,
432  CLK_COR_MAX_LAT_1 => 48,
433  CLK_COR_MIN_LAT_1 => 36,
434  CLK_COR_PRECEDENCE_1 => true,
435  CLK_COR_REPEAT_WAIT_1 => 0,
436  CLK_COR_SEQ_1_1_1 => "1101111100",
437  CLK_COR_SEQ_1_2_1 => "1000111100",
438  CLK_COR_SEQ_1_3_1 => "1000111100",
439  CLK_COR_SEQ_1_4_1 => "1000111100",
440  CLK_COR_SEQ_1_ENABLE_1 => "1111",
441  CLK_COR_SEQ_2_1_1 => "0000000000",
442  CLK_COR_SEQ_2_2_1 => "0000000000",
443  CLK_COR_SEQ_2_3_1 => "0000000000",
444  CLK_COR_SEQ_2_4_1 => "0000000000",
445  CLK_COR_SEQ_2_ENABLE_1 => "0000",
446  CLK_COR_SEQ_2_USE_1 => false,
447  RX_DECODE_SEQ_MATCH_1 => true,
448 
449  ------------------------ Channel Bonding Attributes -------------------
450 
451  CHAN_BOND_1_MAX_SKEW_0 => 1,
452  CHAN_BOND_2_MAX_SKEW_0 => 1,
453  CHAN_BOND_LEVEL_0 => 0,
454  CHAN_BOND_MODE_0 => "OFF",
455  CHAN_BOND_SEQ_1_1_0 => "0000000000",
456  CHAN_BOND_SEQ_1_2_0 => "0000000000",
457  CHAN_BOND_SEQ_1_3_0 => "0000000000",
458  CHAN_BOND_SEQ_1_4_0 => "0000000000",
459  CHAN_BOND_SEQ_1_ENABLE_0 => "0000",
460  CHAN_BOND_SEQ_2_1_0 => "0000000000",
461  CHAN_BOND_SEQ_2_2_0 => "0000000000",
462  CHAN_BOND_SEQ_2_3_0 => "0000000000",
463  CHAN_BOND_SEQ_2_4_0 => "0000000000",
464  CHAN_BOND_SEQ_2_ENABLE_0 => "0000",
465  CHAN_BOND_SEQ_2_USE_0 => false,
466  CHAN_BOND_SEQ_LEN_0 => 1,
467  PCI_EXPRESS_MODE_0 => false,
468 
469  CHAN_BOND_1_MAX_SKEW_1 => 1,
470  CHAN_BOND_2_MAX_SKEW_1 => 1,
471  CHAN_BOND_LEVEL_1 => 0,
472  CHAN_BOND_MODE_1 => "OFF",
473  CHAN_BOND_SEQ_1_1_1 => "0000000000",
474  CHAN_BOND_SEQ_1_2_1 => "0000000000",
475  CHAN_BOND_SEQ_1_3_1 => "0000000000",
476  CHAN_BOND_SEQ_1_4_1 => "0000000000",
477  CHAN_BOND_SEQ_1_ENABLE_1 => "0000",
478  CHAN_BOND_SEQ_2_1_1 => "0000000000",
479  CHAN_BOND_SEQ_2_2_1 => "0000000000",
480  CHAN_BOND_SEQ_2_3_1 => "0000000000",
481  CHAN_BOND_SEQ_2_4_1 => "0000000000",
482  CHAN_BOND_SEQ_2_ENABLE_1 => "0000",
483  CHAN_BOND_SEQ_2_USE_1 => false,
484  CHAN_BOND_SEQ_LEN_1 => 1,
485  PCI_EXPRESS_MODE_1 => false,
486 
487  ------------------ RX Attributes for PCI Express/SATA ---------------
488 
489  RX_STATUS_FMT_0 => "PCIE",
490  SATA_BURST_VAL_0 => "100",
491  SATA_IDLE_VAL_0 => "100",
492  SATA_MAX_BURST_0 => 7,
493  SATA_MAX_INIT_0 => 22,
494  SATA_MAX_WAKE_0 => 7,
495  SATA_MIN_BURST_0 => 4,
496  SATA_MIN_INIT_0 => 12,
497  SATA_MIN_WAKE_0 => 4,
498  TRANS_TIME_FROM_P2_0 => x"0060",
499  TRANS_TIME_NON_P2_0 => x"0025",
500  TRANS_TIME_TO_P2_0 => x"0100",
501 
502  RX_STATUS_FMT_1 => "PCIE",
503  SATA_BURST_VAL_1 => "100",
504  SATA_IDLE_VAL_1 => "100",
505  SATA_MAX_BURST_1 => 7,
506  SATA_MAX_INIT_1 => 22,
507  SATA_MAX_WAKE_1 => 7,
508  SATA_MIN_BURST_1 => 4,
509  SATA_MIN_INIT_1 => 12,
510  SATA_MIN_WAKE_1 => 4,
511  TRANS_TIME_FROM_P2_1 => x"0060",
512  TRANS_TIME_NON_P2_1 => x"0025",
513  TRANS_TIME_TO_P2_1 => x"0100"
514 
515  )
516  port map (
517 
518  ------------------------ Loopback and Powerdown Ports ----------------------
519  LOOPBACK0(0) => '0',
520  LOOPBACK0(1) => gtpLoopback,
521  LOOPBACK0(2) => '0',
522  LOOPBACK1 => "000",
523  RXPOWERDOWN0 => (others => '0'),
524  RXPOWERDOWN1 => (others => '0'),
525  TXPOWERDOWN0 => (others => '0'),
526  TXPOWERDOWN1 => (others => '0'),
527  ----------------------- Receive Ports - 8b10b Decoder ----------------------
528  RXCHARISCOMMA0 => open,
529  RXCHARISCOMMA1 => open,
530  RXCHARISK0(0) => gtpRxDataRaw(8),
531  RXCHARISK0(1) => gtpRxDataRaw(18),
532  RXCHARISK1 => open,
533  RXDEC8B10BUSE0 => '0',
534  RXDEC8B10BUSE1 => '0',
535  RXDISPERR0(0) => gtpRxDataRaw(9),
536  RXDISPERR0(1) => gtpRxDataRaw(19),
537  RXDISPERR1 => open,
538  RXNOTINTABLE0 => open, -- phyRxDecErr,
539  RXNOTINTABLE1 => open,
540  RXRUNDISP0 => open,
541  RXRUNDISP1 => open,
542  ------------------- Receive Ports - Channel Bonding Ports ------------------
543  RXCHANBONDSEQ0 => open,
544  RXCHANBONDSEQ1 => open,
545  RXCHBONDI0 => (others => '0'),
546  RXCHBONDI1 => (others => '0'),
547  RXCHBONDO0 => open,
548  RXCHBONDO1 => open,
549  RXENCHANSYNC0 => '0',
550  RXENCHANSYNC1 => '0',
551  ------------------- Receive Ports - Clock Correction Ports -----------------
552  RXCLKCORCNT0 => open,
553  RXCLKCORCNT1 => open,
554  --------------- Receive Ports - Comma Detection and Alignment --------------
555  RXBYTEISALIGNED0 => open,
556  RXBYTEISALIGNED1 => open,
557  RXBYTEREALIGN0 => open,
558  RXBYTEREALIGN1 => open,
559  RXCOMMADET0 => open,
560  RXCOMMADET1 => open,
561  RXCOMMADETUSE0 => '0',
562  RXCOMMADETUSE1 => '0',
563  RXENMCOMMAALIGN0 => '0',
564  RXENMCOMMAALIGN1 => '0',
565  RXENPCOMMAALIGN0 => '0',
566  RXENPCOMMAALIGN1 => '0',
567  RXSLIDE0 => gtpRxSlide,
568  RXSLIDE1 => '0',
569  ----------------------- Receive Ports - PRBS Detection ---------------------
570  PRBSCNTRESET0 => '0',
571  PRBSCNTRESET1 => '0',
572  RXENPRBSTST0 => (others => '0'),
573  RXENPRBSTST1 => (others => '0'),
574  RXPRBSERR0 => open,
575  RXPRBSERR1 => open,
576  ------------------- Receive Ports - RX Data Path interface -----------------
577  RXDATA0(7 downto 0) => gtpRxDataRaw(7 downto 0),
578  RXDATA0(15 downto 8) => gtpRxDataRaw(17 downto 10),
579  RXDATA1 => open,
580  RXDATAWIDTH0 => '1',
581  RXDATAWIDTH1 => '1',
582  RXRECCLK0 => gtpRxRecClk,
583  RXRECCLK1 => open,
584  RXRESET0 => gtpRxReset,
585  RXRESET1 => '0',
586  RXUSRCLK0 => gtpRxUsrClkInt,
587  RXUSRCLK1 => gtpRxUsrClkInt,
588  RXUSRCLK20 => gtpRxUsrClk2Int,
589  RXUSRCLK21 => gtpRxUsrClk2Int,
590  ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
591  RXCDRRESET0 => gtpRxCdrResetFinal,
592  RXCDRRESET1 => '0',
593  RXELECIDLE0 => gtpRxElecIdle,
594  RXELECIDLE1 => open,
595  RXELECIDLERESET0 => gtpRxElecIdleRst,
596  RXELECIDLERESET1 => '0',
597  RXENEQB0 => '0',
598  RXENEQB1 => '0',
599  RXEQMIX0 => (others => '0'),
600  RXEQMIX1 => (others => '0'),
601  RXEQPOLE0 => (others => '0'),
602  RXEQPOLE1 => (others => '0'),
603  RXN0 => gtpRxN,
604  RXN1 => '1',
605  RXP0 => gtpRxP,
606  RXP1 => '0',
607  -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
608  RXBUFRESET0 => '0',
609  RXBUFRESET1 => '0',
610  RXBUFSTATUS0 => open,
611  RXBUFSTATUS1 => open,
612  RXCHANISALIGNED0 => open,
613  RXCHANISALIGNED1 => open,
614  RXCHANREALIGN0 => open,
615  RXCHANREALIGN1 => open,
616  RXPMASETPHASE0 => '0',
617  RXPMASETPHASE1 => '0',
618  RXSTATUS0 => open,
619  RXSTATUS1 => open,
620  --------------- Receive Ports - RX Loss-of-sync State Machine --------------
621  RXLOSSOFSYNC0 => open,
622  RXLOSSOFSYNC1 => open,
623  ---------------------- Receive Ports - RX Oversampling ---------------------
624  RXENSAMPLEALIGN0 => '0',
625  RXENSAMPLEALIGN1 => '0',
626  RXOVERSAMPLEERR0 => open,
627  RXOVERSAMPLEERR1 => open,
628  -------------- Receive Ports - RX Pipe Control for PCI Express -------------
629  PHYSTATUS0 => open,
630  PHYSTATUS1 => open,
631  RXVALID0 => open,
632  RXVALID1 => open,
633  ----------------- Receive Ports - RX Polarity Control Ports ----------------
634  RXPOLARITY0 => gtpRxPolarity,
635  RXPOLARITY1 => '0',
636  ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
637  DADDR => (others => '0'),
638  DCLK => '0',
639  DEN => '0',
640  DI => (others => '0'),
641  DO => open,
642  DRDY => open,
643  DWE => '0',
644  --------------------- Shared Ports - Tile and PLL Ports --------------------
645  CLKIN => gtpClkIn,
646  GTPRESET => gtpReset,
647  GTPTEST => (others => '0'),
648  INTDATAWIDTH => '1',
649  PLLLKDET => gtpPllLockDetInt,
650  PLLLKDETEN => '1',
651  PLLPOWERDOWN => '0',
652  REFCLKOUT => tmpRefClkOut,
653  REFCLKPWRDNB => '1',
654  RESETDONE0 => gtpResetDone,
655  RESETDONE1 => open,
656  RXENELECIDLERESETB => '1',
657  TXENPMAPHASEALIGN => gtpTxEnPmaPhaseAlign,
658  TXPMASETPHASE => gtpTxPmaSetPhase,
659  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
660  TXBYPASS8B10B0 => (others => '0'),
661  TXBYPASS8B10B1 => (others => '0'),
662  TXCHARDISPMODE0 => (others => '0'),
663  TXCHARDISPMODE1 => (others => '0'),
664  TXCHARDISPVAL0 => (others => '0'),
665  TXCHARDISPVAL1 => (others => '0'),
666  TXCHARISK0 => gtpTxDataK,
667  TXCHARISK1 => "00",
668  TXENC8B10BUSE0 => '1',
669  TXENC8B10BUSE1 => '1',
670  TXKERR0 => open, --txKerr,
671  TXKERR1 => open,
672  TXRUNDISP0 => open,
673  TXRUNDISP1 => open,
674  ------------- Transmit Ports - TX Buffering and Phase Alignment ------------
675  TXBUFSTATUS0 => open, --phyTxBuffStatus,
676  TXBUFSTATUS1 => open,
677  ------------------ Transmit Ports - TX Data Path interface -----------------
678  TXDATA0 => gtpTxData,
679  TXDATA1 => (others => '0'),
680  TXDATAWIDTH0 => '1',
681  TXDATAWIDTH1 => '1',
682  TXOUTCLK0 => open,
683  TXOUTCLK1 => open,
684  TXRESET0 => gtpTxReset,
685  TXRESET1 => '0',
686  TXUSRCLK0 => gtpTxUsrClk,
687  TXUSRCLK1 => gtpTxUsrClk,
688  TXUSRCLK20 => gtpTxUsrClk2,
689  TXUSRCLK21 => gtpTxUsrClk2,
690  --------------- Transmit Ports - TX Driver and OOB signalling --------------
691  TXBUFDIFFCTRL0 => "100", -- 800mV
692  TXBUFDIFFCTRL1 => "100",
693  TXDIFFCTRL0 => "100",
694  TXDIFFCTRL1 => "100",
695  TXINHIBIT0 => '0',
696  TXINHIBIT1 => '0',
697  TXN0 => gtpTxN,
698  TXN1 => open,
699  TXP0 => gtpTxP,
700  TXP1 => open,
701  TXPREEMPHASIS0 => "011", -- 4.5%
702  TXPREEMPHASIS1 => "011",
703  --------------------- Transmit Ports - TX PRBS Generator -------------------
704  TXENPRBSTST0 => (others => '0'),
705  TXENPRBSTST1 => (others => '0'),
706  -------------------- Transmit Ports - TX Polarity Control ------------------
707  TXPOLARITY0 => '0',
708  TXPOLARITY1 => '0',
709  ----------------- Transmit Ports - TX Ports for PCI Express ----------------
710  TXDETECTRX0 => '0',
711  TXDETECTRX1 => '0',
712  TXELECIDLE0 => '0',
713  TXELECIDLE1 => '0',
714  --------------------- Transmit Ports - TX Ports for SATA -------------------
715  TXCOMSTART0 => '0',
716  TXCOMSTART1 => '0',
717  TXCOMTYPE0 => '0',
718  TXCOMTYPE1 => '0'
719  );
720 
721 
722 end rtl;
Decoder8b10b.NUM_BYTES_G
NUM_BYTES_Gpositive := 2
Definition: Decoder8b10b.vhd:29
Decoder8b10b.RST_POLARITY_G
RST_POLARITY_Gsl := '1'
Definition: Decoder8b10b.vhd:30
Gtp16FixedLatCore.gtpTxDataK
in gtpTxDataKslv( 1 downto 0)
Definition: Gtp16FixedLatCore.vhd:88
Gtp16FixedLatCore.gtpTxData
in gtpTxDataslv( 15 downto 0)
Definition: Gtp16FixedLatCore.vhd:86
RstSync.syncRst
out syncRstsl
Definition: RstSync.vhd:36
RstSync.IN_POLARITY_G
IN_POLARITY_Gsl := '1'
Definition: RstSync.vhd:28
GtpRxCommaAligner.gtpRxSlide
out gtpRxSlidestd_logic
Definition: GtpRxCommaAligner.vhd:36
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
Decoder8b10b.TPD_G
TPD_Gtime := 1 ns
Definition: Decoder8b10b.vhd:28
Gtp16FixedLatCore.CLK25_DIVIDER
CLK25_DIVIDERinteger := 5
Definition: Gtp16FixedLatCore.vhd:32
Decoder8b10b.dataOut
out dataOutslv( NUM_BYTES_G* 8- 1 downto 0)
Definition: Decoder8b10b.vhd:38
Gtp16FixedLatCore.REC_CLK_PERIOD
REC_CLK_PERIODreal := 4.000
Definition: Gtp16FixedLatCore.vhd:37
Decoder8b10b.codeErr
out codeErrslv( NUM_BYTES_G- 1 downto 0)
Definition: Decoder8b10b.vhd:41
GtpRxCommaAligner.gtpRxData
in gtpRxDatastd_logic_vector( 19 downto 0)
Definition: GtpRxCommaAligner.vhd:32
Decoder8b10b.dispErr
out dispErrslv( NUM_BYTES_G- 1 downto 0)
Definition: Decoder8b10b.vhd:42
GtpTxPhaseAligner.gtpTxUsrClk2
in gtpTxUsrClk2std_logic
Definition: GtpTxPhaseAligner.vhd:30
GtpTxPhaseAligner.gtpTxEnPmaPhaseAlign
out gtpTxEnPmaPhaseAlignstd_logic
Definition: GtpTxPhaseAligner.vhd:33
RstSync.asyncRst
in asyncRstsl
Definition: RstSync.vhd:35
GtpRxCommaAligner.aligned
out alignedstd_logic
Definition: GtpRxCommaAligner.vhd:38
RstSync.clk
in clksl
Definition: RstSync.vhd:34
Gtp16FixedLatCore.gtpRxDataK
out gtpRxDataKslv( 1 downto 0)
Definition: Gtp16FixedLatCore.vhd:70
RstSync.OUT_POLARITY_G
OUT_POLARITY_Gsl := '1'
Definition: RstSync.vhd:29
GtpRxCommaAligner.gtpRxUsrClk2Sel
out gtpRxUsrClk2Selstd_logic
Definition: GtpRxCommaAligner.vhd:35
Gtp16FixedLatCore.gtpRxData
out gtpRxDataslv( 15 downto 0)
Definition: Gtp16FixedLatCore.vhd:69
GtpTxPhaseAligner.gtpTxPmaSetPhase
out gtpTxPmaSetPhasestd_logic
Definition: GtpTxPhaseAligner.vhd:34
Gtp16FixedLatCore.PLL_DIVSEL_FB
PLL_DIVSEL_FBinteger := 2
Definition: Gtp16FixedLatCore.vhd:33
GtpRxCommaAligner.dispErr
in dispErrstd_logic_vector( 1 downto 0)
Definition: GtpRxCommaAligner.vhd:34
RstSync.RELEASE_DELAY_G
RELEASE_DELAY_Ginteger range 3 to positive'high:= 3
Definition: RstSync.vhd:31
GtpTxPhaseAligner.gtpPllLockDetect
in gtpPllLockDetectstd_logic
Definition: GtpTxPhaseAligner.vhd:32
GtpRxCommaAligner.gtpRxCdrReset
out gtpRxCdrResetstd_logic
Definition: GtpRxCommaAligner.vhd:37
Gtp16FixedLatCore.gtpRxDispErr
out gtpRxDispErrslv( 1 downto 0)
Definition: Gtp16FixedLatCore.vhd:72
Gtp16FixedLatCore.gtpRxDecErr
out gtpRxDecErrslv( 1 downto 0)
Definition: Gtp16FixedLatCore.vhd:71
RstSync.TPD_G
TPD_Gtime := 1 ns
Definition: RstSync.vhd:27
GtpTxPhaseAligner.gtpTxAligned
out gtpTxAlignedstd_logic
Definition: GtpTxPhaseAligner.vhd:35
Decoder8b10b.dataIn
in dataInslv( NUM_BYTES_G* 10- 1 downto 0)
Definition: Decoder8b10b.vhd:37
Decoder8b10b.dataKOut
out dataKOutslv( NUM_BYTES_G- 1 downto 0)
Definition: Decoder8b10b.vhd:39
Gtp16FixedLatCore.PLL_DIVSEL_REF
PLL_DIVSEL_REFinteger := 1
Definition: Gtp16FixedLatCore.vhd:34
Decoder8b10b.rst
in rstsl :=not RST_POLARITY_G
Definition: Decoder8b10b.vhd:35
GtpRxCommaAligner.gtpRxUsrClk2Rst
in gtpRxUsrClk2Rststd_logic
Definition: GtpRxCommaAligner.vhd:31
Gtp16FixedLatCore.SIM_PLL_PERDIV2
SIM_PLL_PERDIV2bit_vector := X"0C8"
Definition: Gtp16FixedLatCore.vhd:31
GtpRxCommaAligner.codeErr
in codeErrstd_logic_vector( 1 downto 0)
Definition: GtpRxCommaAligner.vhd:33
Decoder8b10b.RST_ASYNC_G
RST_ASYNC_Gboolean := false
Definition: Decoder8b10b.vhd:31
GtpRxCommaAligner.gtpRxUsrClk2
in gtpRxUsrClk2std_logic
Definition: GtpRxCommaAligner.vhd:30
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
Gtp16FixedLatCore.REC_PLL_MULT
REC_PLL_MULTinteger := 4
Definition: Gtp16FixedLatCore.vhd:38