SURF  1.0
FifoCascade.vhd
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1 -------------------------------------------------------------------------------
2 -- File : FifoCascade.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2014-04-10
5 -- Last update: 2014-09-23
6 -------------------------------------------------------------------------------
7 -- Description: Wrapper for cascading FWFT FIFOs together
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.numeric_std.all;
21 
22 use work.StdRtlPkg.all;
23 
24 --! @see entity
25  --! @ingroup base_fifo
26 entity FifoCascade is
27  generic (
28  TPD_G : time := 1 ns;
29  CASCADE_SIZE_G : integer range 1 to (2**24) := 1; -- Number of FIFOs to cascade (if set to 1, then no FIFO cascading)
30  LAST_STAGE_ASYNC_G : boolean := true; -- If set to true, the last stage will be the ASYNC FIFO
31  RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low
32  RST_ASYNC_G : boolean := false;
33  GEN_SYNC_FIFO_G : boolean := false;
34  BRAM_EN_G : boolean := true;
35  FWFT_EN_G : boolean := false;
36  USE_DSP48_G : string := "no";
37  ALTERA_SYN_G : boolean := false;
38  ALTERA_RAM_G : string := "M9K";
39  USE_BUILT_IN_G : boolean := false; -- If set to true, this module is only Xilinx compatible only!!!
40  XIL_DEVICE_G : string := "7SERIES"; -- Xilinx only generic parameter
41  SYNC_STAGES_G : integer range 3 to (2**24) := 3;
42  PIPE_STAGES_G : natural range 0 to 16 := 0;
43  DATA_WIDTH_G : integer range 1 to (2**24) := 16;
44  ADDR_WIDTH_G : integer range 4 to 48 := 4;
45  INIT_G : slv := "0";
46  FULL_THRES_G : integer range 1 to (2**24) := 1;
47  EMPTY_THRES_G : integer range 1 to (2**24) := 1);
48  port (
49  -- Resets
50  rst : in sl := '0';
51  --Write Ports (wr_clk domain)
52  wr_clk : in sl;
53  wr_en : in sl := '0';
54  din : in slv(DATA_WIDTH_G-1 downto 0);
55  wr_data_count : out slv(ADDR_WIDTH_G-1 downto 0);
56  wr_ack : out sl;
57  overflow : out sl;
58  prog_full : out sl;
59  almost_full : out sl;
60  full : out sl;
61  not_full : out sl;
62  progFullVec : out slv(CASCADE_SIZE_G-1 downto 0); -- Output stage = 0
63  --Read Ports (rd_clk domain)
64  rd_clk : in sl; --unused if GEN_SYNC_FIFO_G = true
65  rd_en : in sl := '0';
66  dout : out slv(DATA_WIDTH_G-1 downto 0);
67  rd_data_count : out slv(ADDR_WIDTH_G-1 downto 0);
68  valid : out sl;
69  underflow : out sl;
70  prog_empty : out sl;
71  almost_empty : out sl;
72  empty : out sl);
73 end FifoCascade;
74 
75 architecture mapping of FifoCascade is
76 
77  constant GEN_SYNC_FIFO_FIRST_C : boolean := ite(LAST_STAGE_ASYNC_G, true, GEN_SYNC_FIFO_G);
78  constant GEN_SYNC_FIFO_LAST_C : boolean := ite(LAST_STAGE_ASYNC_G, GEN_SYNC_FIFO_G, true);
79  constant CASCADE_SIZE_C : integer := ite((CASCADE_SIZE_G = 1), 0, (CASCADE_SIZE_G-2));
80 
81  type FifoDataType is array (CASCADE_SIZE_C downto 0) of slv((DATA_WIDTH_G-1) downto 0);
82 
83  signal progFull,
84  cascadeClk : sl;
85  signal readJump,
86  validJump,
87  AFullJump : slv(CASCADE_SIZE_C downto 0);
88  signal dataJump : FifoDataType;
89 
90 begin
91 
92  cascadeClk <= wr_clk when(LAST_STAGE_ASYNC_G = true) else rd_clk;
93 
94  -----------------------------------------------------------------
95  -----------------------------------------------------------------
96  -----------------------------------------------------------------
97 
98  ONE_STAGE : if (CASCADE_SIZE_G = 1) generate
99 
100  prog_full <= progFull;
101  progFullVec(0) <= progFull;
102 
103  Fifo_1xStage : entity work.Fifo
104  generic map (
105  TPD_G => TPD_G,
106  RST_POLARITY_G => RST_POLARITY_G,
107  RST_ASYNC_G => RST_ASYNC_G,
108  GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_G,
109  BRAM_EN_G => BRAM_EN_G,
110  FWFT_EN_G => FWFT_EN_G,
111  USE_DSP48_G => USE_DSP48_G,
112  ALTERA_SYN_G => ALTERA_SYN_G,
113  ALTERA_RAM_G => ALTERA_RAM_G,
114  USE_BUILT_IN_G => USE_BUILT_IN_G,
115  XIL_DEVICE_G => XIL_DEVICE_G,
116  SYNC_STAGES_G => SYNC_STAGES_G,
117  PIPE_STAGES_G => PIPE_STAGES_G,
118  DATA_WIDTH_G => DATA_WIDTH_G,
119  ADDR_WIDTH_G => ADDR_WIDTH_G,
120  INIT_G => INIT_G,
121  FULL_THRES_G => FULL_THRES_G,
122  EMPTY_THRES_G => EMPTY_THRES_G)
123  port map (
124  -- Resets
125  rst => rst,
126  --Write Ports (wr_clk domain)
127  wr_clk => wr_clk,
128  wr_en => wr_en,
129  din => din,
130  wr_data_count => wr_data_count,
131  wr_ack => wr_ack,
132  overflow => overflow,
133  prog_full => progFull,
134  almost_full => almost_full,
135  full => full,
136  not_full => not_full,
137  --Read Ports (rd_clk domain)
138  rd_clk => rd_clk,
139  rd_en => rd_en,
140  dout => dout,
141  rd_data_count => rd_data_count,
142  valid => valid,
143  underflow => underflow,
144  prog_empty => prog_empty,
145  almost_empty => almost_empty,
146  empty => empty);
147 
148  end generate;
149 
150  -----------------------------------------------------------------
151  -----------------------------------------------------------------
152  -----------------------------------------------------------------
153 
154  TWO_STAGE : if (CASCADE_SIZE_G >= 2) generate
155 
156  prog_full <= progFull;
157  progFullVec(CASCADE_SIZE_G-1) <= progFull;
158 
159  Fifo_First_Stage : entity work.Fifo
160  generic map (
161  TPD_G => TPD_G,
162  RST_POLARITY_G => RST_POLARITY_G,
163  RST_ASYNC_G => RST_ASYNC_G,
164  GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_FIRST_C,
165  BRAM_EN_G => BRAM_EN_G,
166  FWFT_EN_G => true,
167  USE_DSP48_G => USE_DSP48_G,
168  ALTERA_SYN_G => ALTERA_SYN_G,
169  ALTERA_RAM_G => ALTERA_RAM_G,
170  USE_BUILT_IN_G => USE_BUILT_IN_G,
171  XIL_DEVICE_G => XIL_DEVICE_G,
172  SYNC_STAGES_G => SYNC_STAGES_G,
173  PIPE_STAGES_G => PIPE_STAGES_G,
174  DATA_WIDTH_G => DATA_WIDTH_G,
175  ADDR_WIDTH_G => ADDR_WIDTH_G,
176  INIT_G => INIT_G,
177  FULL_THRES_G => FULL_THRES_G,
178  EMPTY_THRES_G => EMPTY_THRES_G)
179  port map (
180  -- Resets
181  rst => rst,
182  --Write Ports (wr_clk domain)
183  wr_clk => wr_clk,
184  wr_en => wr_en,
185  din => din,
186  wr_data_count => wr_data_count,
187  wr_ack => wr_ack,
188  overflow => overflow,
189  prog_full => progFull,
190  almost_full => almost_full,
191  full => full,
192  not_full => not_full,
193  --Read Ports (rd_clk domain)
194  rd_clk => cascadeClk,
195  rd_en => readJump(CASCADE_SIZE_G-2),
196  dout => dataJump(CASCADE_SIZE_G-2),
197  valid => validJump(CASCADE_SIZE_G-2));
198  readJump(CASCADE_SIZE_G-2) <= validJump(CASCADE_SIZE_G-2) and not AFullJump(CASCADE_SIZE_G-2);
199 
200  MULTI_STAGE : if (CASCADE_SIZE_G > 2) generate
201 
202  GEN_MULTI_STAGE :
203  for i in (CASCADE_SIZE_G-2) downto 1 generate
204 
205  Fifo_Middle_Stage : entity work.Fifo
206  generic map (
207  TPD_G => TPD_G,
208  RST_POLARITY_G => RST_POLARITY_G,
209  RST_ASYNC_G => RST_ASYNC_G,
210  GEN_SYNC_FIFO_G => true,
211  BRAM_EN_G => BRAM_EN_G,
212  FWFT_EN_G => true,
213  USE_DSP48_G => USE_DSP48_G,
214  ALTERA_SYN_G => ALTERA_SYN_G,
215  ALTERA_RAM_G => ALTERA_RAM_G,
216  USE_BUILT_IN_G => USE_BUILT_IN_G,
217  XIL_DEVICE_G => XIL_DEVICE_G,
218  SYNC_STAGES_G => SYNC_STAGES_G,
219  PIPE_STAGES_G => PIPE_STAGES_G,
220  DATA_WIDTH_G => DATA_WIDTH_G,
221  ADDR_WIDTH_G => ADDR_WIDTH_G,
222  INIT_G => INIT_G,
223  FULL_THRES_G => FULL_THRES_G,
224  EMPTY_THRES_G => EMPTY_THRES_G)
225  port map (
226  -- Resets
227  rst => rst,
228  --Write Ports (wr_clk domain)
229  wr_clk => cascadeClk,
230  wr_en => readJump(i),
231  din => dataJump(i),
232  almost_full => AFullJump(i),
233  prog_full => progFullVec(i),
234  --Read Ports (rd_clk domain)
235  rd_clk => cascadeClk,
236  rd_en => readJump(i-1),
237  dout => dataJump(i-1),
238  valid => validJump(i-1));
239  readJump(i-1) <= validJump(i-1) and not AFullJump(i-1);
240 
241  end generate GEN_MULTI_STAGE;
242  end generate;
243 
244  Fifo_Last_Stage : entity work.Fifo
245  generic map (
246  TPD_G => TPD_G,
247  RST_POLARITY_G => RST_POLARITY_G,
248  RST_ASYNC_G => RST_ASYNC_G,
249  GEN_SYNC_FIFO_G => GEN_SYNC_FIFO_LAST_C,
250  BRAM_EN_G => BRAM_EN_G,
251  FWFT_EN_G => FWFT_EN_G,
252  USE_DSP48_G => USE_DSP48_G,
253  ALTERA_SYN_G => ALTERA_SYN_G,
254  ALTERA_RAM_G => ALTERA_RAM_G,
255  USE_BUILT_IN_G => USE_BUILT_IN_G,
256  XIL_DEVICE_G => XIL_DEVICE_G,
257  SYNC_STAGES_G => SYNC_STAGES_G,
258  PIPE_STAGES_G => PIPE_STAGES_G,
259  DATA_WIDTH_G => DATA_WIDTH_G,
260  ADDR_WIDTH_G => ADDR_WIDTH_G,
261  INIT_G => INIT_G,
262  FULL_THRES_G => FULL_THRES_G,
263  EMPTY_THRES_G => EMPTY_THRES_G)
264  port map (
265  -- Resets
266  rst => rst,
267  --Write Ports (wr_clk domain)
268  wr_clk => cascadeClk,
269  wr_en => readJump(0),
270  din => dataJump(0),
271  almost_full => AFullJump(0),
272  prog_full => progFullVec(0),
273  --Read Ports (rd_clk domain)
274  rd_clk => rd_clk,
275  rd_en => rd_en,
276  dout => dout,
277  rd_data_count => rd_data_count,
278  valid => valid,
279  underflow => underflow,
280  prog_empty => prog_empty,
281  almost_empty => almost_empty,
282  empty => empty);
283 
284  end generate;
285 
286 end architecture mapping;
Fifo.SYNC_STAGES_G
SYNC_STAGES_Ginteger range 3 to ( 2** 24):= 3
Definition: Fifo.vhd:39
FifoCascade.almost_full
out almost_fullsl
Definition: FifoCascade.vhd:59
Fifo.din
in dinslv( DATA_WIDTH_G- 1 downto 0)
Definition: Fifo.vhd:52
FifoCascade.ALTERA_RAM_G
ALTERA_RAM_Gstring := "M9K"
Definition: FifoCascade.vhd:38
FifoCascade.valid
out validsl
Definition: FifoCascade.vhd:68
Fifo.almost_empty
out almost_emptysl
Definition: Fifo.vhd:68
FifoCascade.progFullVec
out progFullVecslv( CASCADE_SIZE_G- 1 downto 0)
Definition: FifoCascade.vhd:62
Fifo.wr_data_count
out wr_data_countslv( ADDR_WIDTH_G- 1 downto 0)
Definition: Fifo.vhd:53
FifoCascade.dout
out doutslv( DATA_WIDTH_G- 1 downto 0)
Definition: FifoCascade.vhd:66
Fifo.XIL_DEVICE_G
XIL_DEVICE_Gstring := "7SERIES"
Definition: Fifo.vhd:38
FifoCascade.mapping.readJump
slv( CASCADE_SIZE_C downto 0) readJump
Definition: FifoCascade.vhd:87
Fifo.EMPTY_THRES_G
EMPTY_THRES_Ginteger range 1 to ( 2** 24):= 1
Definition: Fifo.vhd:45
FifoCascade.mapping.GEN_SYNC_FIFO_LAST_C
boolean := ite( LAST_STAGE_ASYNC_G, GEN_SYNC_FIFO_G, true) GEN_SYNC_FIFO_LAST_C
Definition: FifoCascade.vhd:78
FifoCascade.XIL_DEVICE_G
XIL_DEVICE_Gstring := "7SERIES"
Definition: FifoCascade.vhd:40
Fifo.BRAM_EN_G
BRAM_EN_Gboolean := true
Definition: Fifo.vhd:32
FifoCascade.RST_ASYNC_G
RST_ASYNC_Gboolean := false
Definition: FifoCascade.vhd:32
FifoCascade.almost_empty
out almost_emptysl
Definition: FifoCascade.vhd:71
FifoCascade.INIT_G
INIT_Gslv := "0"
Definition: FifoCascade.vhd:45
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
Fifo.FWFT_EN_G
FWFT_EN_Gboolean := false
Definition: Fifo.vhd:33
FifoCascade.mapping.FifoDataType
( CASCADE_SIZE_C downto 0) slv(( DATA_WIDTH_G- 1) downto 0) FifoDataType
Definition: FifoCascade.vhd:81
FifoCascade.BRAM_EN_G
BRAM_EN_Gboolean := true
Definition: FifoCascade.vhd:34
Fifo.empty
out emptysl
Definition: Fifo.vhd:69
FifoAsyncBuiltIn.ieee
_library_ ieeeieee
Definition: FifoAsyncBuiltIn.vhd:18
Fifo.wr_ack
out wr_acksl
Definition: Fifo.vhd:54
Fifo.FULL_THRES_G
FULL_THRES_Ginteger range 1 to ( 2** 24):= 1
Definition: Fifo.vhd:44
FifoCascade.din
in dinslv( DATA_WIDTH_G- 1 downto 0)
Definition: FifoCascade.vhd:54
Fifo.RST_ASYNC_G
RST_ASYNC_Gboolean := false
Definition: Fifo.vhd:30
FifoCascade.mapping.GEN_SYNC_FIFO_FIRST_C
boolean := ite( LAST_STAGE_ASYNC_G, true, GEN_SYNC_FIFO_G) GEN_SYNC_FIFO_FIRST_C
Definition: FifoCascade.vhd:77
Fifo.ALTERA_SYN_G
ALTERA_SYN_Gboolean := false
Definition: Fifo.vhd:35
FifoCascade.rd_clk
in rd_clksl
Definition: FifoCascade.vhd:64
FifoCascade.prog_full
out prog_fullsl
Definition: FifoCascade.vhd:58
Fifo.almost_full
out almost_fullsl
Definition: Fifo.vhd:57
FifoCascade.PIPE_STAGES_G
PIPE_STAGES_Gnatural range 0 to 16:= 0
Definition: FifoCascade.vhd:42
FifoCascade.mapping.dataJump
FifoDataType dataJump
Definition: FifoCascade.vhd:88
Fifo.rd_clk
in rd_clksl
Definition: Fifo.vhd:61
Fifo.USE_DSP48_G
USE_DSP48_Gstring := "no"
Definition: Fifo.vhd:34
FifoCascade.EMPTY_THRES_G
EMPTY_THRES_Ginteger range 1 to ( 2** 24):= 1
Definition: FifoCascade.vhd:47
Fifo.TPD_G
TPD_Gtime := 1 ns
Definition: Fifo.vhd:28
FifoCascade.mapping.AFullJump
slv( CASCADE_SIZE_C downto 0) AFullJump
Definition: FifoCascade.vhd:87
FifoCascade.ALTERA_SYN_G
ALTERA_SYN_Gboolean := false
Definition: FifoCascade.vhd:37
FifoCascade.rd_en
in rd_ensl := '0'
Definition: FifoCascade.vhd:65
FifoCascade.wr_ack
out wr_acksl
Definition: FifoCascade.vhd:56
Fifo.RST_POLARITY_G
RST_POLARITY_Gsl := '1'
Definition: Fifo.vhd:29
FifoCascade.rst
in rstsl := '0'
Definition: FifoCascade.vhd:50
Fifo.DATA_WIDTH_G
DATA_WIDTH_Ginteger range 1 to ( 2** 24):= 16
Definition: Fifo.vhd:41
Fifo.wr_clk
in wr_clksl
Definition: Fifo.vhd:50
FifoCascade.wr_clk
in wr_clksl
Definition: FifoCascade.vhd:52
FifoCascade.overflow
out overflowsl
Definition: FifoCascade.vhd:57
FifoCascade.FULL_THRES_G
FULL_THRES_Ginteger range 1 to ( 2** 24):= 1
Definition: FifoCascade.vhd:46
FifoCascade.SYNC_STAGES_G
SYNC_STAGES_Ginteger range 3 to ( 2** 24):= 3
Definition: FifoCascade.vhd:41
Fifo.full
out fullsl
Definition: Fifo.vhd:58
Fifo.valid
out validsl
Definition: Fifo.vhd:65
Fifo.rd_en
in rd_ensl := '0'
Definition: Fifo.vhd:62
Fifo.underflow
out underflowsl
Definition: Fifo.vhd:66
FifoCascade.mapping.CASCADE_SIZE_C
integer := ite(( CASCADE_SIZE_G= 1), 0,( CASCADE_SIZE_G- 2)) CASCADE_SIZE_C
Definition: FifoCascade.vhd:79
Fifo.overflow
out overflowsl
Definition: Fifo.vhd:55
FifoCascade.wr_en
in wr_ensl := '0'
Definition: FifoCascade.vhd:53
Fifo.ALTERA_RAM_G
ALTERA_RAM_Gstring := "M9K"
Definition: Fifo.vhd:36
FifoCascade.full
out fullsl
Definition: FifoCascade.vhd:60
Fifo.GEN_SYNC_FIFO_G
GEN_SYNC_FIFO_Gboolean := false
Definition: Fifo.vhd:31
Fifo.INIT_G
INIT_Gslv := "0"
Definition: Fifo.vhd:43
FifoCascade.GEN_SYNC_FIFO_G
GEN_SYNC_FIFO_Gboolean := false
Definition: FifoCascade.vhd:33
Fifo.not_full
out not_fullsl
Definition: Fifo.vhd:59
FifoCascade.TPD_G
TPD_Gtime := 1 ns
Definition: FifoCascade.vhd:28
Fifo.dout
out doutslv( DATA_WIDTH_G- 1 downto 0)
Definition: Fifo.vhd:63
Fifo.rst
in rstsl :=not RST_POLARITY_G
Definition: Fifo.vhd:48
Fifo.PIPE_STAGES_G
PIPE_STAGES_Gnatural range 0 to 16:= 0
Definition: Fifo.vhd:40
FifoCascade.USE_DSP48_G
USE_DSP48_Gstring := "no"
Definition: FifoCascade.vhd:36
FifoCascade.LAST_STAGE_ASYNC_G
LAST_STAGE_ASYNC_Gboolean := true
Definition: FifoCascade.vhd:30
Fifo.ADDR_WIDTH_G
ADDR_WIDTH_Ginteger range 4 to 48:= 4
Definition: Fifo.vhd:42
FifoCascade.ADDR_WIDTH_G
ADDR_WIDTH_Ginteger range 4 to 48:= 4
Definition: FifoCascade.vhd:44
Fifo.USE_BUILT_IN_G
USE_BUILT_IN_Gboolean := false
Definition: Fifo.vhd:37
FifoCascade.USE_BUILT_IN_G
USE_BUILT_IN_Gboolean := false
Definition: FifoCascade.vhd:39
FifoCascade.FWFT_EN_G
FWFT_EN_Gboolean := false
Definition: FifoCascade.vhd:35
FifoCascade.not_full
out not_fullsl
Definition: FifoCascade.vhd:61
FifoCascade.DATA_WIDTH_G
DATA_WIDTH_Ginteger range 1 to ( 2** 24):= 16
Definition: FifoCascade.vhd:43
FifoCascade.empty
out emptysl
Definition: FifoCascade.vhd:72
FifoCascade.underflow
out underflowsl
Definition: FifoCascade.vhd:69
FifoCascade.CASCADE_SIZE_G
CASCADE_SIZE_Ginteger range 1 to ( 2** 24):= 1
Definition: FifoCascade.vhd:29
FifoCascade.prog_empty
out prog_emptysl
Definition: FifoCascade.vhd:70
Fifo.prog_full
out prog_fullsl
Definition: Fifo.vhd:56
FifoCascade.wr_data_count
out wr_data_countslv( ADDR_WIDTH_G- 1 downto 0)
Definition: FifoCascade.vhd:55
Fifo.rd_data_count
out rd_data_countslv( ADDR_WIDTH_G- 1 downto 0)
Definition: Fifo.vhd:64
FifoCascade.mapping.validJump
slv( CASCADE_SIZE_C downto 0) validJump
Definition: FifoCascade.vhd:87
Fifo.prog_empty
out prog_emptysl
Definition: Fifo.vhd:67
Fifo
Definition: Fifo.vhd:26
FifoCascade.RST_POLARITY_G
RST_POLARITY_Gsl := '1'
Definition: FifoCascade.vhd:31
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
FifoCascade.rd_data_count
out rd_data_countslv( ADDR_WIDTH_G- 1 downto 0)
Definition: FifoCascade.vhd:67
Fifo.wr_en
in wr_ensl := '0'
Definition: Fifo.vhd:51