SURF  1.0
Dsp48Comparator4x12b.vhd
Go to the documentation of this file.
1 -------------------------------------------------------------------------------
2 -- File : Dsp48Comparator4x12b.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2014-10-02
5 -- Last update: 2014-10-02
6 -------------------------------------------------------------------------------
7 -- Description: This module is a quad 12-bit digital comparator using a DSP48
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 
23 library unisim;
24 use unisim.vcomponents.all;
25 
26 --! @see entity
27  --! @ingroup xilinx_7Series_general
28 entity Dsp48Comparator4x12b is
29  generic (
30  TPD_G : time := 1 ns;
31  EN_GREATER_EQUAL_G : boolean := false); -- true is ">=" operation and false is ">" operation
32  port (
33  -- Data and Threshold Signals
34  polarity : in sl := '0';
35  dataIn : in Slv12Array(0 to 3);
36  threshIn : in Slv12Array(0 to 3);
37  -- Hit detected Signals
38  compOut : out slv(3 downto 0); -- '1' when data > threshold
39  -- Clock and Reset Signals
40  clk : in sl;
41  rst : in sl := '0');
42 end Dsp48Comparator4x12b;
43 
44 architecture mapping of Dsp48Comparator4x12b is
45 
46  signal carryOut : slv(3 downto 0);
47  signal din : slv(47 downto 0);
48  signal A : slv(29 downto 0);
49  signal B : slv(17 downto 0);
50  signal C : slv(47 downto 0);
51  signal reset,
52  rstDly : sl;
53 
54 begin
55 
56  -- Map the data signals into C bus
57  C(47 downto 36) <= dataIn(3);
58  C(35 downto 24) <= dataIn(2);
59  C(23 downto 12) <= dataIn(1);
60  C(11 downto 0) <= dataIn(0);
61 
62  -- Map the threshold signal into A:B bus
63  din(47 downto 36) <= threshIn(3);
64  din(35 downto 24) <= threshIn(2);
65  din(23 downto 12) <= threshIn(1);
66  din(11 downto 0) <= threshIn(0);
67 
68  A <= din(47 downto 18);
69  B <= din(17 downto 0);
70 
71  -- Reduce the fanout of the reset signal to help with timing
72  process(clk)
73  begin
74  if rising_edge(clk) then
75  reset <= rstDly after TPD_G;
76  rstDly <= rst after TPD_G;
77  end if;
78  end process;
79 
80  GEN_HIT :
81  for i in 3 downto 0 generate
82 
83  process(clk)
84  begin
85  if rising_edge(clk) then
86  -- Check for only ">" operation
87  if (EN_GREATER_EQUAL_G = false) and (dataIn(i) = threshIn(i)) then
88  compOut(i) <= '0' after TPD_G;
89  else
90  -- Check the polarity configuration
91  if polarity = '1' then
92  compOut(i) <= not(carryOut(i)) after TPD_G; -- negative pulse polarity
93  else
94  compOut(i) <= carryOut(i) after TPD_G; -- positive pulse polarity
95  end if;
96  end if;
97  end if;
98  end process;
99 
100  end generate GEN_HIT;
101 
102  DSP48E1_Inst : DSP48E1
103  generic map (
104  -- Feature Control Attributes: Data Path Selection
105  A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
106  B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
107  USE_DPORT => false, -- Select D port usage (TRUE or FALSE)
108  USE_MULT => "NONE", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
109  -- Pattern Detector Attributes: Pattern Detection Configuration
110  AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
111  MASK => x"FFFFFFFFFFFF", -- 48-bit mask value for pattern detect (1=ignore)
112  PATTERN => x"000000000000", -- 48-bit pattern match for pattern detect
113  SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
114  SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
115  USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
116  -- Register Control Attributes: Pipeline Register Configuration
117  ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
118  ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
119  ALUMODEREG => 0, -- Number of pipeline stages for ALUMODE (0 or 1)
120  AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
121  BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
122  BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
123  CARRYINREG => 0, -- Number of pipeline stages for CARRYIN (0 or 1)
124  CARRYINSELREG => 0, -- Number of pipeline stages for CARRYINSEL (0 or 1)
125  CREG => 1, -- Number of pipeline stages for C (0 or 1)
126  DREG => 0, -- Number of pipeline stages for D (0 or 1)
127  INMODEREG => 0, -- Number of pipeline stages for INMODE (0 or 1)
128  MREG => 0, -- Number of multiplier pipeline stages (0 or 1)
129  OPMODEREG => 0, -- Number of pipeline stages for OPMODE (0 or 1)
130  PREG => 1, -- Number of pipeline stages for P (0 or 1)
131  USE_SIMD => "FOUR12") -- SIMD selection ("ONE48", "TWO24", "FOUR12")
132  port map (
133  -- Cascade: 30-bit (each) output: Cascade Ports
134  ACOUT => open, -- 30-bit output: A port cascade output
135  BCOUT => open, -- 18-bit output: B port cascade output
136  CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
137  MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
138  PCOUT => open, -- 48-bit output: Cascade output
139  -- Control: 1-bit (each) output: Control Inputs/Status Bits
140  OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
141  PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
142  PATTERNDETECT => open, -- 1-bit output: Pattern detect output
143  UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
144  -- Data: 4-bit (each) output: Data Ports
145  CARRYOUT => carryOut, -- 4-bit output: Carry output
146  P => open, -- 48-bit output: Primary data output
147  -- Cascade: 30-bit (each) input: Cascade Ports
148  ACIN => (others => '0'), -- 30-bit input: A cascade data input
149  BCIN => (others => '0'), -- 18-bit input: B cascade input
150  CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
151  MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
152  PCIN => (others => '0'), -- 48-bit input: P cascade input
153  -- Control: 4-bit (each) input: Control Inputs/Status Bits
154  ALUMODE => "0011", -- 4-bit input: ALU control input
155  CARRYINSEL => "000", -- 3-bit input: Carry select input
156  CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
157  CLK => clk, -- 1-bit input: Clock input
158  INMODE => "00011", -- 5-bit input: INMODE control input
159  OPMODE => "0110011", -- 7-bit input: Operation mode input
160  RSTINMODE => reset, -- 1-bit input: Reset input for INMODEREG
161  -- Data: 30-bit (each) input: Data Ports
162  A => A, -- 30-bit input: A data input
163  B => B, -- 18-bit input: B data input
164  C => C, -- 48-bit input: C data input
165  CARRYIN => '0', -- 1-bit input: Carry input signal
166  D => (others => '0'), -- 25-bit input: D data input
167  -- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
168  CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
169  CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
170  CEAD => '1', -- 1-bit input: Clock enable input for ADREG
171  CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODERE
172  CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
173  CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
174  CEC => '1', -- 1-bit input: Clock enable input for CREG
175  CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
176  CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
177  CED => '1', -- 1-bit input: Clock enable input for DREG
178  CEM => '1', -- 1-bit input: Clock enable input for MREG
179  CEP => '1', -- 1-bit input: Clock enable input for PREG
180  RSTA => reset, -- 1-bit input: Reset input for AREG
181  RSTALLCARRYIN => reset, -- 1-bit input: Reset input for CARRYINREG
182  RSTALUMODE => reset, -- 1-bit input: Reset input for ALUMODEREG
183  RSTB => reset, -- 1-bit input: Reset input for BREG
184  RSTC => reset, -- 1-bit input: Reset input for CREG
185  RSTCTRL => reset, -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
186  RSTD => reset, -- 1-bit input: Reset input for DREG and ADREG
187  RSTM => reset, -- 1-bit input: Reset input for MREG
188  RSTP => reset); -- 1-bit input: Reset input for PREG
189 end mapping;
StdRtlPkg.Slv12Array
array(natural range <> ) of slv( 11 downto 0) Slv12Array
Definition: StdRtlPkg.vhd:399
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
Dsp48Comparator4x12b.compOut
out compOutslv( 3 downto 0)
Definition: Dsp48Comparator4x12b.vhd:38
DeviceDna7Series.ieee
_library_ ieeeieee
Definition: DeviceDna7Series.vhd:18
Dsp48Comparator4x12b.dataIn
in dataInSlv12Array( 0 to 3)
Definition: Dsp48Comparator4x12b.vhd:35
Dsp48Comparator4x12b.threshIn
in threshInSlv12Array( 0 to 3)
Definition: Dsp48Comparator4x12b.vhd:36
Dsp48Comparator4x12b.EN_GREATER_EQUAL_G
EN_GREATER_EQUAL_Gboolean := false
Definition: Dsp48Comparator4x12b.vhd:31
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
DeviceDna7Series.unisim
_library_ unisimunisim
Definition: DeviceDna7Series.vhd:25