SURF  1.0
ClockManager7Pkg.vhd
Go to the documentation of this file.
1 -------------------------------------------------------------------------------
2 -- File : ClockManager7.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2014-10-28
5 -- Last update: 2014-10-29
6 -------------------------------------------------------------------------------
7 -- Description: A wrapper over MMCM/PLL to avoid coregen use.
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.std_logic_unsigned.all;
21 use ieee.std_logic_arith.all;
22 use ieee.math_real.all;
23 
24 library unisim;
25 use unisim.vcomponents.all;
26 
27 use work.StdRtlPkg.all;
28 
29 package ClockManager7Pkg is
30 --! @file
31  --! @ingroup xilinx_7Series_general
32  type ClockManager7CfgType is record
33  CLKIN_PERIOD_G : real;
34  DIVCLK_DIVIDE_G : integer range 1 to 106;
35  CLKFBOUT_MULT_F_G : real range 1.0 to 64.0;
36  CLKFBOUT_MULT_G : integer range 2 to 64;
37  CLKOUT0_DIVIDE_F_G : real range 1.0 to 128.0;
38  CLKOUT0_DIVIDE_G : integer range 1 to 128;
39  CLKOUT1_DIVIDE_G : integer range 1 to 128;
40  CLKOUT2_DIVIDE_G : integer range 1 to 128;
41  CLKOUT3_DIVIDE_G : integer range 1 to 128;
42  CLKOUT4_DIVIDE_G : integer range 1 to 128;
43  CLKOUT5_DIVIDE_G : integer range 1 to 128;
44  CLKOUT6_DIVIDE_G : integer range 1 to 128;
45  CLKOUT0_PHASE_G : real range -360.0 to 360.0;
46  CLKOUT1_PHASE_G : real range -360.0 to 360.0;
47  CLKOUT2_PHASE_G : real range -360.0 to 360.0;
48  CLKOUT3_PHASE_G : real range -360.0 to 360.0;
49  CLKOUT4_PHASE_G : real range -360.0 to 360.0;
50  CLKOUT5_PHASE_G : real range -360.0 to 360.0;
51  CLKOUT6_PHASE_G : real range -360.0 to 360.0;
52  CLKOUT0_DUTY_CYCLE_G : real range 0.01 to 0.99;
53  CLKOUT1_DUTY_CYCLE_G : real range 0.01 to 0.99;
54  CLKOUT2_DUTY_CYCLE_G : real range 0.01 to 0.99;
55  CLKOUT3_DUTY_CYCLE_G : real range 0.01 to 0.99;
56  CLKOUT4_DUTY_CYCLE_G : real range 0.01 to 0.99;
57  CLKOUT5_DUTY_CYCLE_G : real range 0.01 to 0.99;
58  CLKOUT6_DUTY_CYCLE_G : real range 0.01 to 0.99;
59  CLKOUT0_RST_HOLD_G : integer range 3 to positive'high;
60  CLKOUT1_RST_HOLD_G : integer range 3 to positive'high;
61  CLKOUT2_RST_HOLD_G : integer range 3 to positive'high;
62  CLKOUT3_RST_HOLD_G : integer range 3 to positive'high;
63  CLKOUT4_RST_HOLD_G : integer range 3 to positive'high;
64  CLKOUT5_RST_HOLD_G : integer range 3 to positive'high;
65  CLKOUT6_RST_HOLD_G : integer range 3 to positive'high;
66  CLKOUT0_RST_POLARITY_G : sl;
67  CLKOUT1_RST_POLARITY_G : sl;
68  CLKOUT2_RST_POLARITY_G : sl;
69  CLKOUT3_RST_POLARITY_G : sl;
70  CLKOUT4_RST_POLARITY_G : sl;
71  CLKOUT5_RST_POLARITY_G : sl;
72  CLKOUT6_RST_POLARITY_G : sl;
73  end record;
74 
75  type ClockManager7CfgArray is array (natural range <>) of ClockManager7CfgType;
76 
77 .......-...-...-...-...-...-...-........................ function makeClockManager7Cfg (
78  CLKIN_PERIOD_G : real := 100; -- Input period in ns );
79  DIVCLK_DIVIDE_G : integer range 1 to 106 := 1;
80  CLKFBOUT_MULT_F_G : real range 10 to 640 := 10;
81  CLKFBOUT_MULT_G : integer range 2 to 64 := 5;
82  CLKOUT0_DIVIDE_F_G : real range 10 to 1280 := 10;
83  CLKOUT0_DIVIDE_G : integer range 1 to 128 := 1;
84  CLKOUT1_DIVIDE_G : integer range 1 to 128 := 1;
85  CLKOUT2_DIVIDE_G : integer range 1 to 128 := 1;
86  CLKOUT3_DIVIDE_G : integer range 1 to 128 := 1;
87  CLKOUT4_DIVIDE_G : integer range 1 to 128 := 1;
88  CLKOUT5_DIVIDE_G : integer range 1 to 128 := 1;
89  CLKOUT6_DIVIDE_G : integer range 1 to 128 := 1;
90  CLKOUT0_PHASE_G : real range 3600 to 3600 := 00;
91  CLKOUT1_PHASE_G : real range 3600 to 3600 := 00;
92  CLKOUT2_PHASE_G : real range 3600 to 3600 := 00;
93  CLKOUT3_PHASE_G : real range 3600 to 3600 := 00;
94  CLKOUT4_PHASE_G : real range 3600 to 3600 := 00;
95  CLKOUT5_PHASE_G : real range 3600 to 3600 := 00;
96  CLKOUT6_PHASE_G : real range 3600 to 3600 := 00;
97  CLKOUT0_DUTY_CYCLE_G : real range 001 to 099 := 05;
98  CLKOUT1_DUTY_CYCLE_G : real range 001 to 099 := 05;
99  CLKOUT2_DUTY_CYCLE_G : real range 001 to 099 := 05;
100  CLKOUT3_DUTY_CYCLE_G : real range 001 to 099 := 05;
101  CLKOUT4_DUTY_CYCLE_G : real range 001 to 099 := 05;
102  CLKOUT5_DUTY_CYCLE_G : real range 001 to 099 := 05;
103  CLKOUT6_DUTY_CYCLE_G : real range 001 to 099 := 05;
104  CLKOUT0_RST_HOLD_G : integer range 3 to positive'high := 3;
105  CLKOUT1_RST_HOLD_G : integer range 3 to positive'high := 3;
106  CLKOUT2_RST_HOLD_G : integer range 3 to positive'high := 3;
107  CLKOUT3_RST_HOLD_G : integer range 3 to positive'high := 3;
108  CLKOUT4_RST_HOLD_G : integer range 3 to positive'high := 3;
109  CLKOUT5_RST_HOLD_G : integer range 3 to positive'high := 3;
110  CLKOUT6_RST_HOLD_G : integer range 3 to positive'high := 3;
111  CLKOUT0_RST_POLARITY_G : sl := '1';
112  CLKOUT1_RST_POLARITY_G : sl := '1';
113  CLKOUT2_RST_POLARITY_G : sl := '1';
114  CLKOUT3_RST_POLARITY_G : sl := '1';
115  CLKOUT4_RST_POLARITY_G : sl := '1';
116  CLKOUT5_RST_POLARITY_G : sl := '1';
117  CLKOUT6_RST_POLARITY_G : sl := '1')
118  return ClockManager7CfgType;
119 
120 --
121 -- DIVCLK_DIVIDE_G : integer range 1 to 106;
122 -- CLKFBOUT_MULT_F_G : real range 1.0 to 64.0;
123 -- CLKFBOUT_MULT_G : integer range 2 to 64;
124 -- CLKOUT0_DIVIDE_F_G : real range 1.0 to 128.0;
125 -- CLKOUT0_DIVIDE_G : integer range 1 to 128;
126 -- CLKOUT1_DIVIDE_G : integer range 1 to 128;
127 -- CLKOUT2_DIVIDE_G : integer range 1 to 128;
128 -- CLKOUT3_DIVIDE_G : integer range 1 to 128;
129 -- CLKOUT4_DIVIDE_G : integer range 1 to 128;
130 -- CLKOUT5_DIVIDE_G : integer range 1 to 128;
131 -- CLKOUT6_DIVIDE_G : integer range 1 to 128;
132 -- end record ClockManager7CfgType;
133 
134  function ite (i : boolean; t : ClockManager7CfgType; e : ClockManager7CfgType) return ClockManager7CfgType;
135 
136 end package ClockManager7Pkg;
137 
138 package body ClockManager7Pkg is
139 
140 .......-...-...-...-...-...-...-........................ function makeClockManager7Cfg (
141  CLKIN_PERIOD_G : real := 100;
142  DIVCLK_DIVIDE_G : integer range 1 to 106 := 1;
143  CLKFBOUT_MULT_F_G : real range 10 to 640 := 10;
144  CLKFBOUT_MULT_G : integer range 2 to 64 := 5;
145  CLKOUT0_DIVIDE_F_G : real range 10 to 1280 := 10;
146  CLKOUT0_DIVIDE_G : integer range 1 to 128 := 1;
147  CLKOUT1_DIVIDE_G : integer range 1 to 128 := 1;
148  CLKOUT2_DIVIDE_G : integer range 1 to 128 := 1;
149  CLKOUT3_DIVIDE_G : integer range 1 to 128 := 1;
150  CLKOUT4_DIVIDE_G : integer range 1 to 128 := 1;
151  CLKOUT5_DIVIDE_G : integer range 1 to 128 := 1;
152  CLKOUT6_DIVIDE_G : integer range 1 to 128 := 1;
153  CLKOUT0_PHASE_G : real range 3600 to 3600 := 00;
154  CLKOUT1_PHASE_G : real range 3600 to 3600 := 00;
155  CLKOUT2_PHASE_G : real range 3600 to 3600 := 00;
156  CLKOUT3_PHASE_G : real range 3600 to 3600 := 00;
157  CLKOUT4_PHASE_G : real range 3600 to 3600 := 00;
158  CLKOUT5_PHASE_G : real range 3600 to 3600 := 00;
159  CLKOUT6_PHASE_G : real range 3600 to 3600 := 00;
160  CLKOUT0_DUTY_CYCLE_G : real range 001 to 099 := 05;
161  CLKOUT1_DUTY_CYCLE_G : real range 001 to 099 := 05;
162  CLKOUT2_DUTY_CYCLE_G : real range 001 to 099 := 05;
163  CLKOUT3_DUTY_CYCLE_G : real range 001 to 099 := 05;
164  CLKOUT4_DUTY_CYCLE_G : real range 001 to 099 := 05;
165  CLKOUT5_DUTY_CYCLE_G : real range 001 to 099 := 05;
166  CLKOUT6_DUTY_CYCLE_G : real range 001 to 099 := 05;
167  CLKOUT0_RST_HOLD_G : integer range 3 to positive'high := 3;
168  CLKOUT1_RST_HOLD_G : integer range 3 to positive'high := 3;
169  CLKOUT2_RST_HOLD_G : integer range 3 to positive'high := 3;
170  CLKOUT3_RST_HOLD_G : integer range 3 to positive'high := 3;
171  CLKOUT4_RST_HOLD_G : integer range 3 to positive'high := 3;
172  CLKOUT5_RST_HOLD_G : integer range 3 to positive'high := 3;
173  CLKOUT6_RST_HOLD_G : integer range 3 to positive'high := 3;
174  CLKOUT0_RST_POLARITY_G : sl := '1';
175  CLKOUT1_RST_POLARITY_G : sl := '1';
176  CLKOUT2_RST_POLARITY_G : sl := '1';
177  CLKOUT3_RST_POLARITY_G : sl := '1';
178  CLKOUT4_RST_POLARITY_G : sl := '1';
179  CLKOUT5_RST_POLARITY_G : sl := '1';
180  CLKOUT6_RST_POLARITY_G : sl := '1')
181  return ClockManager7CfgType
182  is
183  variable ret : ClockManager7CfgType;
184  begin
185  ret.CLKIN_PERIOD_G := CLKIN_PERIOD_G;
186  ret.DIVCLK_DIVIDE_G := DIVCLK_DIVIDE_G;
187  ret.CLKFBOUT_MULT_F_G := CLKFBOUT_MULT_F_G;
188  ret.CLKFBOUT_MULT_G := CLKFBOUT_MULT_G;
189  ret.CLKOUT0_DIVIDE_F_G := CLKOUT0_DIVIDE_F_G;
190  ret.CLKOUT0_DIVIDE_G := CLKOUT0_DIVIDE_G;
191  ret.CLKOUT1_DIVIDE_G := CLKOUT1_DIVIDE_G;
192  ret.CLKOUT2_DIVIDE_G := CLKOUT2_DIVIDE_G;
193  ret.CLKOUT3_DIVIDE_G := CLKOUT3_DIVIDE_G;
194  ret.CLKOUT4_DIVIDE_G := CLKOUT4_DIVIDE_G;
195  ret.CLKOUT5_DIVIDE_G := CLKOUT5_DIVIDE_G;
196  ret.CLKOUT6_DIVIDE_G := CLKOUT6_DIVIDE_G;
197  ret.CLKOUT0_PHASE_G := CLKOUT0_PHASE_G;
198  ret.CLKOUT1_PHASE_G := CLKOUT1_PHASE_G;
199  ret.CLKOUT2_PHASE_G := CLKOUT2_PHASE_G;
200  ret.CLKOUT3_PHASE_G := CLKOUT3_PHASE_G;
201  ret.CLKOUT4_PHASE_G := CLKOUT4_PHASE_G;
202  ret.CLKOUT5_PHASE_G := CLKOUT5_PHASE_G;
203  ret.CLKOUT6_PHASE_G := CLKOUT6_PHASE_G;
204  ret.CLKOUT0_DUTY_CYCLE_G := CLKOUT0_DUTY_CYCLE_G;
205  ret.CLKOUT1_DUTY_CYCLE_G := CLKOUT1_DUTY_CYCLE_G;
206  ret.CLKOUT2_DUTY_CYCLE_G := CLKOUT2_DUTY_CYCLE_G;
207  ret.CLKOUT3_DUTY_CYCLE_G := CLKOUT3_DUTY_CYCLE_G;
208  ret.CLKOUT4_DUTY_CYCLE_G := CLKOUT4_DUTY_CYCLE_G;
209  ret.CLKOUT5_DUTY_CYCLE_G := CLKOUT5_DUTY_CYCLE_G;
210  ret.CLKOUT6_DUTY_CYCLE_G := CLKOUT6_DUTY_CYCLE_G;
211  ret.CLKOUT0_RST_HOLD_G := CLKOUT0_RST_HOLD_G;
212  ret.CLKOUT1_RST_HOLD_G := CLKOUT1_RST_HOLD_G;
213  ret.CLKOUT2_RST_HOLD_G := CLKOUT2_RST_HOLD_G;
214  ret.CLKOUT3_RST_HOLD_G := CLKOUT3_RST_HOLD_G;
215  ret.CLKOUT4_RST_HOLD_G := CLKOUT4_RST_HOLD_G;
216  ret.CLKOUT5_RST_HOLD_G := CLKOUT5_RST_HOLD_G;
217  ret.CLKOUT6_RST_HOLD_G := CLKOUT6_RST_HOLD_G;
218  ret.CLKOUT0_RST_POLARITY_G := CLKOUT0_RST_POLARITY_G;
219  ret.CLKOUT1_RST_POLARITY_G := CLKOUT1_RST_POLARITY_G;
220  ret.CLKOUT2_RST_POLARITY_G := CLKOUT2_RST_POLARITY_G;
221  ret.CLKOUT3_RST_POLARITY_G := CLKOUT3_RST_POLARITY_G;
222  ret.CLKOUT4_RST_POLARITY_G := CLKOUT4_RST_POLARITY_G;
223  ret.CLKOUT5_RST_POLARITY_G := CLKOUT5_RST_POLARITY_G;
224  ret.CLKOUT6_RST_POLARITY_G := CLKOUT6_RST_POLARITY_G;
225  return ret;
226  end function makeClockManager7Cfg;
227 
228  function ite (i : boolean; t : ClockManager7CfgType; e : ClockManager7CfgType) return ClockManager7CfgType is
229  begin
230  if (i) then return t; else return e; end if;
231  end function ite;
232 
233 end package body ClockManager7Pkg;
ClockManager7Pkg.CLKFBOUT_MULT_G
integer range 2 to 64 CLKFBOUT_MULT_G
Definition: ClockManager7Pkg.vhd:36
ClockManager7Pkg.CLKOUT4_PHASE_G
real range - 360.0 to 360.0 CLKOUT4_PHASE_G
Definition: ClockManager7Pkg.vhd:49
ClockManager7Pkg.CLKOUT1_DUTY_CYCLE_G
real range 0.01 to 0.99 CLKOUT1_DUTY_CYCLE_G
Definition: ClockManager7Pkg.vhd:53
ClockManager7Pkg.CLKOUT5_DUTY_CYCLE_G
real range 0.01 to 0.99 CLKOUT5_DUTY_CYCLE_G
Definition: ClockManager7Pkg.vhd:57
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
ClockManager7Pkg.CLKOUT5_DIVIDE_G
integer range 1 to 128 CLKOUT5_DIVIDE_G
Definition: ClockManager7Pkg.vhd:43
ClockManager7Pkg.CLKOUT6_DIVIDE_G
integer range 1 to 128 CLKOUT6_DIVIDE_G
Definition: ClockManager7Pkg.vhd:44
ClockManager7Pkg.CLKOUT3_PHASE_G
real range - 360.0 to 360.0 CLKOUT3_PHASE_G
Definition: ClockManager7Pkg.vhd:48
ClockManager7Pkg.DIVCLK_DIVIDE_G
integer range 1 to 106 DIVCLK_DIVIDE_G
Definition: ClockManager7Pkg.vhd:34
ClockManager7Pkg.CLKOUT4_DUTY_CYCLE_G
real range 0.01 to 0.99 CLKOUT4_DUTY_CYCLE_G
Definition: ClockManager7Pkg.vhd:56
ClockManager7Pkg.CLKOUT6_PHASE_G
real range - 360.0 to 360.0 CLKOUT6_PHASE_G
Definition: ClockManager7Pkg.vhd:51
ClockManager7Pkg.CLKOUT2_PHASE_G
real range - 360.0 to 360.0 CLKOUT2_PHASE_G
Definition: ClockManager7Pkg.vhd:47
ClockManager7Pkg.ClockManager7CfgArray
array(natural range <> ) of ClockManager7CfgType ClockManager7CfgArray
Definition: ClockManager7Pkg.vhd:75
ClockManager7Pkg.CLKOUT4_DIVIDE_G
integer range 1 to 128 CLKOUT4_DIVIDE_G
Definition: ClockManager7Pkg.vhd:42
ClockManager7Pkg.CLKOUT3_RST_HOLD_G
integer range 3 to positive'high CLKOUT3_RST_HOLD_G
Definition: ClockManager7Pkg.vhd:62
ClockManager7Pkg.CLKOUT5_PHASE_G
real range - 360.0 to 360.0 CLKOUT5_PHASE_G
Definition: ClockManager7Pkg.vhd:50
ClockManager7Pkg.CLKOUT1_RST_HOLD_G
integer range 3 to positive'high CLKOUT1_RST_HOLD_G
Definition: ClockManager7Pkg.vhd:60
ClockManager7Pkg.makeClockManager7Cfg
ClockManager7CfgType makeClockManager7CfgCLKIN_PERIOD_G,DIVCLK_DIVIDE_G,CLKFBOUT_MULT_F_G,CLKFBOUT_MULT_G,CLKOUT0_DIVIDE_F_G,CLKOUT0_DIVIDE_G,CLKOUT1_DIVIDE_G,CLKOUT2_DIVIDE_G,CLKOUT3_DIVIDE_G,CLKOUT4_DIVIDE_G,CLKOUT5_DIVIDE_G,CLKOUT6_DIVIDE_G,CLKOUT0_PHASE_G,CLKOUT1_PHASE_G,CLKOUT2_PHASE_G,CLKOUT3_PHASE_G,CLKOUT4_PHASE_G,CLKOUT5_PHASE_G,CLKOUT6_PHASE_G,CLKOUT0_DUTY_CYCLE_G,CLKOUT1_DUTY_CYCLE_G,CLKOUT2_DUTY_CYCLE_G,CLKOUT3_DUTY_CYCLE_G,CLKOUT4_DUTY_CYCLE_G,CLKOUT5_DUTY_CYCLE_G,CLKOUT6_DUTY_CYCLE_G,CLKOUT0_RST_HOLD_G,CLKOUT1_RST_HOLD_G,CLKOUT2_RST_HOLD_G,CLKOUT3_RST_HOLD_G,CLKOUT4_RST_HOLD_G,CLKOUT5_RST_HOLD_G,CLKOUT6_RST_HOLD_G,CLKOUT0_RST_POLARITY_G,CLKOUT1_RST_POLARITY_G,CLKOUT2_RST_POLARITY_G,CLKOUT3_RST_POLARITY_G,CLKOUT4_RST_POLARITY_G,CLKOUT5_RST_POLARITY_G,CLKOUT6_RST_POLARITY_G,
Definition: ClockManager7Pkg.vhd:77
ClockManager7Pkg.CLKOUT0_DIVIDE_G
integer range 1 to 128 CLKOUT0_DIVIDE_G
Definition: ClockManager7Pkg.vhd:38
ClockManager7Pkg.CLKOUT2_DUTY_CYCLE_G
real range 0.01 to 0.99 CLKOUT2_DUTY_CYCLE_G
Definition: ClockManager7Pkg.vhd:54
ClockManager7Pkg.CLKOUT0_DIVIDE_F_G
real range 1.0 to 128.0 CLKOUT0_DIVIDE_F_G
Definition: ClockManager7Pkg.vhd:37
ClockManager7Pkg.CLKOUT3_DIVIDE_G
integer range 1 to 128 CLKOUT3_DIVIDE_G
Definition: ClockManager7Pkg.vhd:41
ClockManager7.ieee
_library_ ieeeieee
Definition: ClockManager7.vhd:18
ClockManager7Pkg.CLKOUT1_DIVIDE_G
integer range 1 to 128 CLKOUT1_DIVIDE_G
Definition: ClockManager7Pkg.vhd:39
ClockManager7Pkg.CLKFBOUT_MULT_F_G
real range 1.0 to 64.0 CLKFBOUT_MULT_F_G
Definition: ClockManager7Pkg.vhd:35
ClockManager7Pkg.CLKOUT5_RST_HOLD_G
integer range 3 to positive'high CLKOUT5_RST_HOLD_G
Definition: ClockManager7Pkg.vhd:64
ClockManager7Pkg.CLKOUT3_DUTY_CYCLE_G
real range 0.01 to 0.99 CLKOUT3_DUTY_CYCLE_G
Definition: ClockManager7Pkg.vhd:55
ClockManager7Pkg.CLKOUT6_DUTY_CYCLE_G
real range 0.01 to 0.99 CLKOUT6_DUTY_CYCLE_G
Definition: ClockManager7Pkg.vhd:58
ClockManager7Pkg.CLKOUT2_DIVIDE_G
integer range 1 to 128 CLKOUT2_DIVIDE_G
Definition: ClockManager7Pkg.vhd:40
ClockManager7Pkg.CLKOUT1_PHASE_G
real range - 360.0 to 360.0 CLKOUT1_PHASE_G
Definition: ClockManager7Pkg.vhd:46
ClockManager7Pkg.ite
ClockManager7CfgType itei,t,e,
Definition: ClockManager7Pkg.vhd:134
ClockManager7Pkg.CLKOUT6_RST_HOLD_G
integer range 3 to positive'high CLKOUT6_RST_HOLD_G
Definition: ClockManager7Pkg.vhd:65
ClockManager7Pkg.CLKOUT0_PHASE_G
real range - 360.0 to 360.0 CLKOUT0_PHASE_G
Definition: ClockManager7Pkg.vhd:45
ClockManager7Pkg.CLKOUT4_RST_HOLD_G
integer range 3 to positive'high CLKOUT4_RST_HOLD_G
Definition: ClockManager7Pkg.vhd:63
ClockManager7Pkg.CLKOUT0_RST_HOLD_G
integer range 3 to positive'high CLKOUT0_RST_HOLD_G
Definition: ClockManager7Pkg.vhd:59
ClockManager7.unisim
_library_ unisimunisim
Definition: ClockManager7.vhd:24
ClockManager7Pkg.CLKOUT0_DUTY_CYCLE_G
real range 0.01 to 0.99 CLKOUT0_DUTY_CYCLE_G
Definition: ClockManager7Pkg.vhd:52
ClockManager7Pkg.CLKOUT2_RST_HOLD_G
integer range 3 to positive'high CLKOUT2_RST_HOLD_G
Definition: ClockManager7Pkg.vhd:61