SURF  1.0
Libraries | Use Clauses | Records | Types | Functions
ClockManager7Pkg Package Reference
Package Body >> ClockManager7Pkg

Functions

ClockManager7CfgType   makeClockManager7Cfg (
CLKIN_PERIOD_G: in real 10.0
DIVCLK_DIVIDE_G: in integer range 1 to 106 1
CLKFBOUT_MULT_F_G: in real range 1.0 to 64.0 1.0
CLKFBOUT_MULT_G: in integer range 2 to 64 5
CLKOUT0_DIVIDE_F_G: in real range 1.0 to 128.0 1.0
CLKOUT0_DIVIDE_G: in integer range 1 to 128 1
CLKOUT1_DIVIDE_G: in integer range 1 to 128 1
CLKOUT2_DIVIDE_G: in integer range 1 to 128 1
CLKOUT3_DIVIDE_G: in integer range 1 to 128 1
CLKOUT4_DIVIDE_G: in integer range 1 to 128 1
CLKOUT5_DIVIDE_G: in integer range 1 to 128 1
CLKOUT6_DIVIDE_G: in integer range 1 to 128 1
CLKOUT0_PHASE_G: in real range - 360.0 to 360.0 0.0
CLKOUT1_PHASE_G: in real range - 360.0 to 360.0 0.0
CLKOUT2_PHASE_G: in real range - 360.0 to 360.0 0.0
CLKOUT3_PHASE_G: in real range - 360.0 to 360.0 0.0
CLKOUT4_PHASE_G: in real range - 360.0 to 360.0 0.0
CLKOUT5_PHASE_G: in real range - 360.0 to 360.0 0.0
CLKOUT6_PHASE_G: in real range - 360.0 to 360.0 0.0
CLKOUT0_DUTY_CYCLE_G: in real range 0.01 to 0.99 0.5
CLKOUT1_DUTY_CYCLE_G: in real range 0.01 to 0.99 0.5
CLKOUT2_DUTY_CYCLE_G: in real range 0.01 to 0.99 0.5
CLKOUT3_DUTY_CYCLE_G: in real range 0.01 to 0.99 0.5
CLKOUT4_DUTY_CYCLE_G: in real range 0.01 to 0.99 0.5
CLKOUT5_DUTY_CYCLE_G: in real range 0.01 to 0.99 0.5
CLKOUT6_DUTY_CYCLE_G: in real range 0.01 to 0.99 0.5
CLKOUT0_RST_HOLD_G: in integer range 3 to positive'high 3
CLKOUT1_RST_HOLD_G: in integer range 3 to positive'high 3
CLKOUT2_RST_HOLD_G: in integer range 3 to positive'high 3
CLKOUT3_RST_HOLD_G: in integer range 3 to positive'high 3
CLKOUT4_RST_HOLD_G: in integer range 3 to positive'high 3
CLKOUT5_RST_HOLD_G: in integer range 3 to positive'high 3
CLKOUT6_RST_HOLD_G: in integer range 3 to positive'high 3
CLKOUT0_RST_POLARITY_G: in sl '1'
CLKOUT1_RST_POLARITY_G: in sl '1'
CLKOUT2_RST_POLARITY_G: in sl '1'
CLKOUT3_RST_POLARITY_G: in sl '1'
CLKOUT4_RST_POLARITY_G: in sl '1'
CLKOUT5_RST_POLARITY_G: in sl '1'
CLKOUT6_RST_POLARITY_G: in sl '1'
)
ClockManager7CfgType   ite (
i: in boolean
t: in ClockManager7CfgType
e: in ClockManager7CfgType
)

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
math_real 
vcomponents 
StdRtlPkg  Package <StdRtlPkg>

Types

ClockManager7CfgArray array ( natural range <> ) of ClockManager7CfgType

Records

ClockManager7CfgType  
CLKIN_PERIOD_G  real
DIVCLK_DIVIDE_G  integer range 1 to 106
CLKFBOUT_MULT_F_G  real range 1 . 0 to 64 . 0
CLKFBOUT_MULT_G  integer range 2 to 64
CLKOUT0_DIVIDE_F_G  real range 1 . 0 to 128 . 0
CLKOUT0_DIVIDE_G  integer range 1 to 128
CLKOUT1_DIVIDE_G  integer range 1 to 128
CLKOUT2_DIVIDE_G  integer range 1 to 128
CLKOUT3_DIVIDE_G  integer range 1 to 128
CLKOUT4_DIVIDE_G  integer range 1 to 128
CLKOUT5_DIVIDE_G  integer range 1 to 128
CLKOUT6_DIVIDE_G  integer range 1 to 128
CLKOUT0_PHASE_G  real range - 360 . 0 to 360 . 0
CLKOUT1_PHASE_G  real range - 360 . 0 to 360 . 0
CLKOUT2_PHASE_G  real range - 360 . 0 to 360 . 0
CLKOUT3_PHASE_G  real range - 360 . 0 to 360 . 0
CLKOUT4_PHASE_G  real range - 360 . 0 to 360 . 0
CLKOUT5_PHASE_G  real range - 360 . 0 to 360 . 0
CLKOUT6_PHASE_G  real range - 360 . 0 to 360 . 0
CLKOUT0_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99
CLKOUT1_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99
CLKOUT2_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99
CLKOUT3_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99
CLKOUT4_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99
CLKOUT5_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99
CLKOUT6_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99
CLKOUT0_RST_HOLD_G  integer range 3 to positive ' high
CLKOUT1_RST_HOLD_G  integer range 3 to positive ' high
CLKOUT2_RST_HOLD_G  integer range 3 to positive ' high
CLKOUT3_RST_HOLD_G  integer range 3 to positive ' high
CLKOUT4_RST_HOLD_G  integer range 3 to positive ' high
CLKOUT5_RST_HOLD_G  integer range 3 to positive ' high
CLKOUT6_RST_HOLD_G  integer range 3 to positive ' high
CLKOUT0_RST_POLARITY_G  sl
CLKOUT1_RST_POLARITY_G  sl
CLKOUT2_RST_POLARITY_G  sl
CLKOUT3_RST_POLARITY_G  sl
CLKOUT4_RST_POLARITY_G  sl
CLKOUT5_RST_POLARITY_G  sl
CLKOUT6_RST_POLARITY_G  sl

Detailed Description

Definition at line 29 of file ClockManager7Pkg.vhd.

Member Function Documentation

◆ makeClockManager7Cfg()

ClockManager7CfgType makeClockManager7Cfg (   CLKIN_PERIOD_G in real 10 . 0 ,
  DIVCLK_DIVIDE_G in integer range 1 to 106 1 ,
  CLKFBOUT_MULT_F_G in real range 1 . 0 to 64 . 0 1 . 0 ,
  CLKFBOUT_MULT_G in integer range 2 to 64 5 ,
  CLKOUT0_DIVIDE_F_G in real range 1 . 0 to 128 . 0 1 . 0 ,
  CLKOUT0_DIVIDE_G in integer range 1 to 128 1 ,
  CLKOUT1_DIVIDE_G in integer range 1 to 128 1 ,
  CLKOUT2_DIVIDE_G in integer range 1 to 128 1 ,
  CLKOUT3_DIVIDE_G in integer range 1 to 128 1 ,
  CLKOUT4_DIVIDE_G in integer range 1 to 128 1 ,
  CLKOUT5_DIVIDE_G in integer range 1 to 128 1 ,
  CLKOUT6_DIVIDE_G in integer range 1 to 128 1 ,
  CLKOUT0_PHASE_G in real range - 360 . 0 to 360 . 0 0 . 0 ,
  CLKOUT1_PHASE_G in real range - 360 . 0 to 360 . 0 0 . 0 ,
  CLKOUT2_PHASE_G in real range - 360 . 0 to 360 . 0 0 . 0 ,
  CLKOUT3_PHASE_G in real range - 360 . 0 to 360 . 0 0 . 0 ,
  CLKOUT4_PHASE_G in real range - 360 . 0 to 360 . 0 0 . 0 ,
  CLKOUT5_PHASE_G in real range - 360 . 0 to 360 . 0 0 . 0 ,
  CLKOUT6_PHASE_G in real range - 360 . 0 to 360 . 0 0 . 0 ,
  CLKOUT0_DUTY_CYCLE_G in real range 0 . 01 to 0 . 99 0 . 5 ,
  CLKOUT1_DUTY_CYCLE_G in real range 0 . 01 to 0 . 99 0 . 5 ,
  CLKOUT2_DUTY_CYCLE_G in real range 0 . 01 to 0 . 99 0 . 5 ,
  CLKOUT3_DUTY_CYCLE_G in real range 0 . 01 to 0 . 99 0 . 5 ,
  CLKOUT4_DUTY_CYCLE_G in real range 0 . 01 to 0 . 99 0 . 5 ,
  CLKOUT5_DUTY_CYCLE_G in real range 0 . 01 to 0 . 99 0 . 5 ,
  CLKOUT6_DUTY_CYCLE_G in real range 0 . 01 to 0 . 99 0 . 5 ,
  CLKOUT0_RST_HOLD_G in integer range 3 to positive'high 3 ,
  CLKOUT1_RST_HOLD_G in integer range 3 to positive'high 3 ,
  CLKOUT2_RST_HOLD_G in integer range 3 to positive'high 3 ,
  CLKOUT3_RST_HOLD_G in integer range 3 to positive'high 3 ,
  CLKOUT4_RST_HOLD_G in integer range 3 to positive'high 3 ,
  CLKOUT5_RST_HOLD_G in integer range 3 to positive'high 3 ,
  CLKOUT6_RST_HOLD_G in integer range 3 to positive'high 3 ,
  CLKOUT0_RST_POLARITY_G in sl ' 1 ' ,
  CLKOUT1_RST_POLARITY_G in sl ' 1 ' ,
  CLKOUT2_RST_POLARITY_G in sl ' 1 ' ,
  CLKOUT3_RST_POLARITY_G in sl ' 1 ' ,
  CLKOUT4_RST_POLARITY_G in sl ' 1 ' ,
  CLKOUT5_RST_POLARITY_G in sl ' 1 ' ,
  CLKOUT6_RST_POLARITY_G in sl ' 1 '  
)
Function

Definition at line 77 of file ClockManager7Pkg.vhd.

◆ ite()

ClockManager7CfgType ite (   i in boolean ,
  t in ClockManager7CfgType ,
  e in ClockManager7CfgType  
)
Function

Definition at line 134 of file ClockManager7Pkg.vhd.

Member Data Documentation

◆ ieee

ieee
Library

Definition at line 18 of file ClockManager7Pkg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file ClockManager7Pkg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file ClockManager7Pkg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file ClockManager7Pkg.vhd.

◆ math_real

math_real
Package

Definition at line 22 of file ClockManager7Pkg.vhd.

◆ unisim

unisim
Library

Definition at line 24 of file ClockManager7Pkg.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 25 of file ClockManager7Pkg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 27 of file ClockManager7Pkg.vhd.

◆ ClockManager7CfgType

ClockManager7CfgType
Record

Definition at line 32 of file ClockManager7Pkg.vhd.

◆ CLKIN_PERIOD_G

CLKIN_PERIOD_G real
Record

Definition at line 33 of file ClockManager7Pkg.vhd.

◆ DIVCLK_DIVIDE_G

DIVCLK_DIVIDE_G integer range 1 to 106
Record

Definition at line 34 of file ClockManager7Pkg.vhd.

◆ CLKFBOUT_MULT_F_G

CLKFBOUT_MULT_F_G real range 1 . 0 to 64 . 0
Record

Definition at line 35 of file ClockManager7Pkg.vhd.

◆ CLKFBOUT_MULT_G

CLKFBOUT_MULT_G integer range 2 to 64
Record

Definition at line 36 of file ClockManager7Pkg.vhd.

◆ CLKOUT0_DIVIDE_F_G

CLKOUT0_DIVIDE_F_G real range 1 . 0 to 128 . 0
Record

Definition at line 37 of file ClockManager7Pkg.vhd.

◆ CLKOUT0_DIVIDE_G

CLKOUT0_DIVIDE_G integer range 1 to 128
Record

Definition at line 38 of file ClockManager7Pkg.vhd.

◆ CLKOUT1_DIVIDE_G

CLKOUT1_DIVIDE_G integer range 1 to 128
Record

Definition at line 39 of file ClockManager7Pkg.vhd.

◆ CLKOUT2_DIVIDE_G

CLKOUT2_DIVIDE_G integer range 1 to 128
Record

Definition at line 40 of file ClockManager7Pkg.vhd.

◆ CLKOUT3_DIVIDE_G

CLKOUT3_DIVIDE_G integer range 1 to 128
Record

Definition at line 41 of file ClockManager7Pkg.vhd.

◆ CLKOUT4_DIVIDE_G

CLKOUT4_DIVIDE_G integer range 1 to 128
Record

Definition at line 42 of file ClockManager7Pkg.vhd.

◆ CLKOUT5_DIVIDE_G

CLKOUT5_DIVIDE_G integer range 1 to 128
Record

Definition at line 43 of file ClockManager7Pkg.vhd.

◆ CLKOUT6_DIVIDE_G

CLKOUT6_DIVIDE_G integer range 1 to 128
Record

Definition at line 44 of file ClockManager7Pkg.vhd.

◆ CLKOUT0_PHASE_G

CLKOUT0_PHASE_G real range - 360 . 0 to 360 . 0
Record

Definition at line 45 of file ClockManager7Pkg.vhd.

◆ CLKOUT1_PHASE_G

CLKOUT1_PHASE_G real range - 360 . 0 to 360 . 0
Record

Definition at line 46 of file ClockManager7Pkg.vhd.

◆ CLKOUT2_PHASE_G

CLKOUT2_PHASE_G real range - 360 . 0 to 360 . 0
Record

Definition at line 47 of file ClockManager7Pkg.vhd.

◆ CLKOUT3_PHASE_G

CLKOUT3_PHASE_G real range - 360 . 0 to 360 . 0
Record

Definition at line 48 of file ClockManager7Pkg.vhd.

◆ CLKOUT4_PHASE_G

CLKOUT4_PHASE_G real range - 360 . 0 to 360 . 0
Record

Definition at line 49 of file ClockManager7Pkg.vhd.

◆ CLKOUT5_PHASE_G

CLKOUT5_PHASE_G real range - 360 . 0 to 360 . 0
Record

Definition at line 50 of file ClockManager7Pkg.vhd.

◆ CLKOUT6_PHASE_G

CLKOUT6_PHASE_G real range - 360 . 0 to 360 . 0
Record

Definition at line 51 of file ClockManager7Pkg.vhd.

◆ CLKOUT0_DUTY_CYCLE_G

CLKOUT0_DUTY_CYCLE_G real range 0 . 01 to 0 . 99
Record

Definition at line 52 of file ClockManager7Pkg.vhd.

◆ CLKOUT1_DUTY_CYCLE_G

CLKOUT1_DUTY_CYCLE_G real range 0 . 01 to 0 . 99
Record

Definition at line 53 of file ClockManager7Pkg.vhd.

◆ CLKOUT2_DUTY_CYCLE_G

CLKOUT2_DUTY_CYCLE_G real range 0 . 01 to 0 . 99
Record

Definition at line 54 of file ClockManager7Pkg.vhd.

◆ CLKOUT3_DUTY_CYCLE_G

CLKOUT3_DUTY_CYCLE_G real range 0 . 01 to 0 . 99
Record

Definition at line 55 of file ClockManager7Pkg.vhd.

◆ CLKOUT4_DUTY_CYCLE_G

CLKOUT4_DUTY_CYCLE_G real range 0 . 01 to 0 . 99
Record

Definition at line 56 of file ClockManager7Pkg.vhd.

◆ CLKOUT5_DUTY_CYCLE_G

CLKOUT5_DUTY_CYCLE_G real range 0 . 01 to 0 . 99
Record

Definition at line 57 of file ClockManager7Pkg.vhd.

◆ CLKOUT6_DUTY_CYCLE_G

CLKOUT6_DUTY_CYCLE_G real range 0 . 01 to 0 . 99
Record

Definition at line 58 of file ClockManager7Pkg.vhd.

◆ CLKOUT0_RST_HOLD_G

CLKOUT0_RST_HOLD_G integer range 3 to positive ' high
Record

Definition at line 59 of file ClockManager7Pkg.vhd.

◆ CLKOUT1_RST_HOLD_G

CLKOUT1_RST_HOLD_G integer range 3 to positive ' high
Record

Definition at line 60 of file ClockManager7Pkg.vhd.

◆ CLKOUT2_RST_HOLD_G

CLKOUT2_RST_HOLD_G integer range 3 to positive ' high
Record

Definition at line 61 of file ClockManager7Pkg.vhd.

◆ CLKOUT3_RST_HOLD_G

CLKOUT3_RST_HOLD_G integer range 3 to positive ' high
Record

Definition at line 62 of file ClockManager7Pkg.vhd.

◆ CLKOUT4_RST_HOLD_G

CLKOUT4_RST_HOLD_G integer range 3 to positive ' high
Record

Definition at line 63 of file ClockManager7Pkg.vhd.

◆ CLKOUT5_RST_HOLD_G

CLKOUT5_RST_HOLD_G integer range 3 to positive ' high
Record

Definition at line 64 of file ClockManager7Pkg.vhd.

◆ CLKOUT6_RST_HOLD_G

CLKOUT6_RST_HOLD_G integer range 3 to positive ' high
Record

Definition at line 65 of file ClockManager7Pkg.vhd.

◆ CLKOUT0_RST_POLARITY_G

CLKOUT0_RST_POLARITY_G sl
Record

Definition at line 66 of file ClockManager7Pkg.vhd.

◆ CLKOUT1_RST_POLARITY_G

CLKOUT1_RST_POLARITY_G sl
Record

Definition at line 67 of file ClockManager7Pkg.vhd.

◆ CLKOUT2_RST_POLARITY_G

CLKOUT2_RST_POLARITY_G sl
Record

Definition at line 68 of file ClockManager7Pkg.vhd.

◆ CLKOUT3_RST_POLARITY_G

CLKOUT3_RST_POLARITY_G sl
Record

Definition at line 69 of file ClockManager7Pkg.vhd.

◆ CLKOUT4_RST_POLARITY_G

CLKOUT4_RST_POLARITY_G sl
Record

Definition at line 70 of file ClockManager7Pkg.vhd.

◆ CLKOUT5_RST_POLARITY_G

CLKOUT5_RST_POLARITY_G sl
Record

Definition at line 71 of file ClockManager7Pkg.vhd.

◆ CLKOUT6_RST_POLARITY_G

CLKOUT6_RST_POLARITY_G sl
Record

Definition at line 72 of file ClockManager7Pkg.vhd.

◆ ClockManager7CfgArray

ClockManager7CfgArray array ( natural range <> ) of ClockManager7CfgType
Type

Definition at line 75 of file ClockManager7Pkg.vhd.

The documentation for this class was generated from the following file: