SURF  1.0
AxiSy56040Pkg.vhd
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1 -------------------------------------------------------------------------------
2 -- File : AxiSy56040Pkg.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-06-12
5 -- Last update: 2015-06-12
6 -------------------------------------------------------------------------------
7 -- Description: AxiSy56040 Package File
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 
23 package AxiSy56040Pkg is
24 --! @file
25  --! @ingroup devices_Microchip_sy56040
26 
27  type AxiSy56040OutType is record
28  sin : slv(1 downto 0);
29  sout : slv(1 downto 0);
30  config : sl;
31  load : sl;
32  end record;
33  type AxiSy56040OutArray is array (natural range <>) of AxiSy56040OutType;
34  type AxiSy56040OutVectorArray is array (integer range<>, integer range<>)of AxiSy56040OutType;
35 
36 end package;
std_logic sl
Definition: StdRtlPkg.vhd:28
array(natural range <> ) of AxiSy56040OutType AxiSy56040OutArray
slv( 1 downto 0) sin
array(integer range <> ,integer range <> ) of AxiSy56040OutType AxiSy56040OutVectorArray
slv( 1 downto 0) sout
_library_ ieeeieee
std_logic_vector slv
Definition: StdRtlPkg.vhd:29