SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiSy56040Core Entity Reference
devices » Microchip » sy56040
+ Inheritance diagram for AxiSy56040Core:
+ Collaboration diagram for AxiSy56040Core:

Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiSy56040Pkg  Package <AxiSy56040Pkg>

Generics

TPD_G  time := 1 ns
AXI_CLK_FREQ_G  real := 200 . 0E + 6
XBAR_DEFAULT_G  Slv2Array ( 3 downto 0 ) := ( " 11 " , " 10 " , " 01 " , " 00 " )
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

xBar   out AxiSy56040OutType
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl

Detailed Description

See also
entity

Definition at line 27 of file AxiSy56040Core.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file AxiSy56040Core.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 30 of file AxiSy56040Core.vhd.

◆ XBAR_DEFAULT_G

XBAR_DEFAULT_G Slv2Array ( 3 downto 0 ) := ( " 11 " , " 10 " , " 01 " , " 00 " )
Generic

Definition at line 31 of file AxiSy56040Core.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 32 of file AxiSy56040Core.vhd.

◆ xBar

xBar out AxiSy56040OutType
Port

Definition at line 35 of file AxiSy56040Core.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 37 of file AxiSy56040Core.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 38 of file AxiSy56040Core.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 39 of file AxiSy56040Core.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 40 of file AxiSy56040Core.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 42 of file AxiSy56040Core.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 43 of file AxiSy56040Core.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiSy56040Core.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiSy56040Core.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file AxiSy56040Core.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 22 of file AxiSy56040Core.vhd.

◆ AxiSy56040Pkg

AxiSy56040Pkg
Package

Definition at line 23 of file AxiSy56040Core.vhd.

The documentation for this class was generated from the following file: