1 ------------------------------------------------------------------------------- 2 -- File : AxiStreamDmaRingPkg.vhd 3 -- Company : SLAC National Accelerator Laboratory 4 -- Created : 2016-03-08 5 -- Last update: 2016-08-02 6 ------------------------------------------------------------------------------- 7 -- Description: AxiStreamDmaRingPkg Support Package 8 ------------------------------------------------------------------------------- 9 -- This file is part of SLAC Firmware Standard Library. It is subject to 10 -- the license terms in the LICENSE.txt file found in the top-level directory 11 -- of this distribution and at: 12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 13 -- No part of SLAC Firmware Standard Library, including this file, may be 14 -- copied, modified, propagated, or distributed except according to the terms 15 -- contained in the LICENSE.txt file. 16 ------------------------------------------------------------------------------- 19 use ieee.std_logic_1164.
all;
20 use ieee.std_logic_arith.
all;
21 use ieee.std_logic_unsigned.
all;
45 subtype FST_C is range 31 downto 16;
53 subtype FAT_C is range 31 downto 16;
60 baseAddr :
slv(
31 downto 0);
61 busIndex :
range 0 to 7;
62 buf :
slv(
5 downto 0) := (
others => '0');
67 baseAddr :
slv(
31 downto 0);
68 busIndex :
range 0 to 7;
69 buf :
range 0 to 63 :=
0;
78 TKEEP_MODE_C => TKEEP_FIXED_C, --ite(BSA_STREAM_BYTE_WIDTH_G = 4, TKEEP_FIXED_C, TKEEP_COMP_C), 82 end package AxiStreamDmaRingPkg;
87 baseAddr :
slv(
31 downto 0);
88 busIndex :
range 0 to 7;
89 buf :
slv(
5 downto 0) := (
others => '0');
93 variable ret :
slv(31 downto 0);
95 ret := baseAddr
(31 downto 12) & toSlv
(busIndex,
3) & buf &
high &
"00";
97 ret := baseAddr
(31 downto 12) & toSlv
(busIndex,
3) & '
0' & buf &
"00";
103 baseAddr :
slv(
31 downto 0);
104 busIndex :
range 0 to 7;
105 buf :
range 0 to 63 :=
0;
109 return getBufferAddr
(baseAddr, busIndex, toSlv
(buf,
6),
high);
112 -- function getAxilConfig ( 113 -- baseAddr : slv(31 downto 0); 114 -- busIndex : integer) 115 -- return AxiLiteCrossbarMasterConfigType 117 -- variable ret : AxiLiteCrossbarMasterConfigType; 120 -- end function getAxilConfig; 122 end package body AxiStreamDmaRingPkg;
natural range 0 to 8 TDEST_BITS_C
integer := INIT_C/ 8 INIT_BYTE_C
integer := 5 STATUS_AXIL_C
integer range 31 downto 16 FST_C
natural range 1 to 16 TDATA_BYTES_C
integer := 6 AXIL_MASTERS_C
slv( 7 downto 0) := X"18" BUFFER_CLEAR_OFFSET_C
TkeepModeType TKEEP_MODE_C
slv getBufferAddrbaseAddr,busIndex,buf,high,
AxiStreamConfigType :=(TSTRB_EN_C => false,TDATA_BYTES_C => 1,TDEST_BITS_C => 0,TID_BITS_C => 0,TKEEP_MODE_C => TKEEP_FIXED_C,TUSER_BITS_C => 1,TUSER_MODE_C => TUSER_NONE_C) DMA_RING_STATUS_CONFIG_C
natural range 0 to 8 TID_BITS_C
integer := 1 DONE_WHEN_FULL_C
TUserModeType TUSER_MODE_C
integer := 0 START_AXIL_C
natural range 0 to 8 TUSER_BITS_C
integer range 11 downto 8 BURST_SIZE_C
integer := 3 SOFT_TRIGGER_C
integer range 31 downto 16 FAT_C
integer range 7 downto 4 STATUS_TDEST_C