SURF  1.0
AxiStreamDmaRingPkg.vhd
Go to the documentation of this file.
1 -------------------------------------------------------------------------------
2 -- File : AxiStreamDmaRingPkg.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2016-03-08
5 -- Last update: 2016-08-02
6 -------------------------------------------------------------------------------
7 -- Description: AxiStreamDmaRingPkg Support Package
8 -------------------------------------------------------------------------------
9 -- This file is part of SLAC Firmware Standard Library. It is subject to
10 -- the license terms in the LICENSE.txt file found in the top-level directory
11 -- of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of SLAC Firmware Standard Library, including this file, may be
14 -- copied, modified, propagated, or distributed except according to the terms
15 -- contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.std_logic_arith.all;
21 use ieee.std_logic_unsigned.all;
22 
23 use work.StdRtlPkg.all;
24 use work.AxiStreamPkg.all;
25 
27 --! @file
28  --! @ingroup axi
29 
30  constant AXIL_MASTERS_C : integer := 6;
31  constant START_AXIL_C : integer := 0;
32  constant END_AXIL_C : integer := 1;
33  constant NEXT_AXIL_C : integer := 2;
34  constant TRIG_AXIL_C : integer := 3;
35  constant MODE_AXIL_C : integer := 4;
36  constant STATUS_AXIL_C : integer := 5;
37 
38  -- Status constants
39  constant EMPTY_C : integer := 0;
40  constant FULL_C : integer := 1;
41  constant DONE_C : integer := 2;
42  constant TRIGGERED_C : integer := 3;
43  constant ERROR_C : integer := 4;
44  subtype BURST_SIZE_C is integer range 11 downto 8;
45  subtype FST_C is integer range 31 downto 16;
46 
47  -- Mode constants
48  constant ENABLED_C : integer := 0; -- Not currently used
49  constant DONE_WHEN_FULL_C : integer := 1;
50  constant INIT_C : integer := 2;
51  constant SOFT_TRIGGER_C : integer := 3;
52  subtype STATUS_TDEST_C is integer range 7 downto 4;
53  subtype FAT_C is integer range 31 downto 16;
54 
55  constant INIT_BYTE_C : integer := INIT_C / 8;
56 
57  constant BUFFER_CLEAR_OFFSET_C : slv(7 downto 0) := X"18";
58 
59  function getBufferAddr (
60  baseAddr : slv(31 downto 0);
61  busIndex : integer range 0 to 7;
62  buf : slv(5 downto 0) := (others => '0');
63  high : sl := '0')
64  return slv;
65 
66  function getBufferAddr (
67  baseAddr : slv(31 downto 0);
68  busIndex : integer range 0 to 7;
69  buf : integer range 0 to 63 := 0;
70  high : sl := '0')
71  return slv;
72 
74  TSTRB_EN_C => false,
75  TDATA_BYTES_C => 1,
76  TDEST_BITS_C => 0,
77  TID_BITS_C => 0,
78  TKEEP_MODE_C => TKEEP_FIXED_C, --ite(BSA_STREAM_BYTE_WIDTH_G = 4, TKEEP_FIXED_C, TKEEP_COMP_C),
79  TUSER_BITS_C => 1,
80  TUSER_MODE_C => TUSER_NONE_C);
81 
82 end package AxiStreamDmaRingPkg;
83 
84 package body AxiStreamDmaRingPkg is
85 
86  function getBufferAddr (
87  baseAddr : slv(31 downto 0);
88  busIndex : integer range 0 to 7;
89  buf : slv(5 downto 0) := (others => '0');
90  high : sl := '0')
91  return slv
92  is
93  variable ret : slv(31 downto 0);
94  begin
95  ret := baseAddr(31 downto 12) & toSlv(busIndex, 3) & buf & high & "00";
96  if (busIndex = MODE_AXIL_C or busIndex = STATUS_AXIL_C) then
97  ret := baseAddr(31 downto 12) & toSlv(busIndex, 3) & '0' & buf & "00";
98  end if;
99  return ret;
100  end function;
101 
102  function getBufferAddr (
103  baseAddr : slv(31 downto 0);
104  busIndex : integer range 0 to 7;
105  buf : integer range 0 to 63 := 0;
106  high : sl := '0')
107  return slv
108  is begin
109  return getBufferAddr(baseAddr, busIndex, toSlv(buf, 6), high);
110  end function;
111 
112 -- function getAxilConfig (
113 -- baseAddr : slv(31 downto 0);
114 -- busIndex : integer)
115 -- return AxiLiteCrossbarMasterConfigType
116 -- is
117 -- variable ret : AxiLiteCrossbarMasterConfigType;
118 -- begin
119 
120 -- end function getAxilConfig;
121 
122 end package body AxiStreamDmaRingPkg;
123 
natural range 0 to 8 TDEST_BITS_C
integer := INIT_C/ 8 INIT_BYTE_C
std_logic sl
Definition: StdRtlPkg.vhd:28
integer range 31 downto 16 FST_C
natural range 1 to 16 TDATA_BYTES_C
slv( 7 downto 0) := X"18" BUFFER_CLEAR_OFFSET_C
TkeepModeType TKEEP_MODE_C
slv getBufferAddrbaseAddr,busIndex,buf,high,
AxiStreamConfigType :=(TSTRB_EN_C => false,TDATA_BYTES_C => 1,TDEST_BITS_C => 0,TID_BITS_C => 0,TKEEP_MODE_C => TKEEP_FIXED_C,TUSER_BITS_C => 1,TUSER_MODE_C => TUSER_NONE_C) DMA_RING_STATUS_CONFIG_C
natural range 0 to 8 TID_BITS_C
boolean TSTRB_EN_C
TUserModeType TUSER_MODE_C
natural range 0 to 8 TUSER_BITS_C
_library_ ieeeieee
integer range 11 downto 8 BURST_SIZE_C
integer range 31 downto 16 FAT_C
integer range 7 downto 4 STATUS_TDEST_C
std_logic_vector slv
Definition: StdRtlPkg.vhd:29