SURF  1.0
AxiAd5780Pkg.vhd
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1 -------------------------------------------------------------------------------
2 -- File : AxiAd5780Pkg.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2014-04-18
5 -- Last update: 2017-05-02
6 -------------------------------------------------------------------------------
7 -- Description: AD5780 Package File
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 
23 package AxiAd5780Pkg is
24 --! @file
25  --! @ingroup devices_AnalogDevices_ad5780
26 
27  type AxiAd5780InType is record
29  end record;
30  type AxiAd5780InArray is array (natural range <>) of AxiAd5780InType;
31  type AxiAd5780InVectorArray is array (integer range<>, integer range<>)of AxiAd5780InType;
32  constant AXI_AD5780_IN_INIT_C : AxiAd5780InType := (dacSdo => '1');
33 
34  type AxiAd5780OutType is record
41  end record;
42  type AxiAd5780OutArray is array (natural range <>) of AxiAd5780OutType;
43  type AxiAd5780OutVectorArray is array (integer range<>, integer range<>)of AxiAd5780OutType;
45  '1',
46  '1',
47  '1',
48  '1',
49  '1',
50  '1');
51 
52  type AxiAd5780StatusType is record
54  dacData : slv(17 downto 0); -- 2's complement by default
55  end record;
57  '0',
58  (others => '0'));
59 
60  type AxiAd5780ConfigType is record
61  halfSckPeriod : slv(31 downto 0);
65  opGnd : sl;
66  rbuf : sl;
68  debugData : slv(17 downto 0); -- 2's complement by default
69  end record;
71  (others => '1'),
72  '1',
73  '0',
74  '0',
75  '0',
76  '1',
77  '0',
78  (others => '0'));
79 
80 end package;
array(integer range <> ,integer range <> ) of AxiAd5780OutType AxiAd5780OutVectorArray
std_logic sl
Definition: StdRtlPkg.vhd:28
AxiAd5780OutType :=( '1', '1', '1', '1', '1', '1') AXI_AD5780_OUT_INIT_C
array(integer range <> ,integer range <> ) of AxiAd5780InType AxiAd5780InVectorArray
AxiAd5780InType :=(dacSdo => '1') AXI_AD5780_IN_INIT_C
AxiAd5780StatusType :=( '0',( others => '0')) AXI_AD5780_STATUS_INIT_C
slv( 17 downto 0) debugData
slv( 17 downto 0) dacData
AxiAd5780ConfigType :=(( others => '1'), '1', '0', '0', '0', '1', '0',( others => '0')) AXI_AD5780_CONFIG_INIT_C
slv( 31 downto 0) halfSckPeriod
array(natural range <> ) of AxiAd5780InType AxiAd5780InArray
array(natural range <> ) of AxiAd5780OutType AxiAd5780OutArray
_library_ ieeeieee
std_logic_vector slv
Definition: StdRtlPkg.vhd:29