SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiAd5780Core Entity Reference
devices » AnalogDevices » ad5780
+ Inheritance diagram for AxiAd5780Core:
+ Collaboration diagram for AxiAd5780Core:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiAd5780Pkg  Package <AxiAd5780Pkg>

Generics

TPD_G  time := 1 ns
STATUS_CNT_WIDTH_G  natural range 1 to 32 := 32
USE_DSP48_G  string := " no "
AXI_CLK_FREQ_G  real := 200 . 0E + 6
SPI_CLK_FREQ_G  real := 25 . 0E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

dacIn   in AxiAd5780InType
dacOut   out AxiAd5780OutType
dacData   in slv ( 17 downto 0 )
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl

Detailed Description

See also
entity

Definition at line 27 of file AxiAd5780Core.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file AxiAd5780Core.vhd.

◆ STATUS_CNT_WIDTH_G

STATUS_CNT_WIDTH_G natural range 1 to 32 := 32
Generic

Definition at line 30 of file AxiAd5780Core.vhd.

◆ USE_DSP48_G

USE_DSP48_G string := " no "
Generic

Definition at line 31 of file AxiAd5780Core.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 32 of file AxiAd5780Core.vhd.

◆ SPI_CLK_FREQ_G

SPI_CLK_FREQ_G real := 25 . 0E + 6
Generic

Definition at line 33 of file AxiAd5780Core.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 34 of file AxiAd5780Core.vhd.

◆ dacIn

dacIn in AxiAd5780InType
Port

Definition at line 37 of file AxiAd5780Core.vhd.

◆ dacOut

dacOut out AxiAd5780OutType
Port

Definition at line 38 of file AxiAd5780Core.vhd.

◆ dacData

dacData in slv ( 17 downto 0 )
Port

Definition at line 40 of file AxiAd5780Core.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 42 of file AxiAd5780Core.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 43 of file AxiAd5780Core.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 44 of file AxiAd5780Core.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 45 of file AxiAd5780Core.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 47 of file AxiAd5780Core.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 48 of file AxiAd5780Core.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiAd5780Core.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiAd5780Core.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file AxiAd5780Core.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 22 of file AxiAd5780Core.vhd.

◆ AxiAd5780Pkg

AxiAd5780Pkg
Package

Definition at line 23 of file AxiAd5780Core.vhd.

The documentation for this class was generated from the following file: