SURF  1.0
Ad9249Deserializer.vhd
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1 -------------------------------------------------------------------------------
2 -- File : Ad9249Deserializer.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2013-02-22
5 -- Last update: 2016-06-10
6 -------------------------------------------------------------------------------
7 -- Description: 14 bit DDR deserializer using 7 series IDELAYE2 and ISERDESE2.
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 
19 library ieee;
20 use ieee.std_logic_1164.all;
21 use work.StdRtlPkg.all;
22 library UNISIM;
23 use UNISIM.vcomponents.all;
24 
25 --! @see entity
26  --! @ingroup devices_AnalogDevices_ad9249
27 entity Ad9249Deserializer is
28 
29  generic (
30  TPD_G : time := 1 ns;
31  IODELAY_GROUP_G : string;
32  IDELAYCTRL_FREQ_G : real := 200.0);
33  port (
34  clkIo : in sl;
35  clkIoInv : in sl;
36  clkR : in sl;
37  rst : in sl;
38  slip : in sl;
39 
40  sysClk : in sl;
41  curDelay : out slv(4 downto 0);
42  setDelay : in slv(4 downto 0);
43  setValid : in sl;
44 
45  iData : in sl;
46  oData : out slv(13 downto 0));
47 
48 end entity Ad9249Deserializer;
49 
50 architecture rtl of Ad9249Deserializer is
51 
52  signal dlyData : sl;
53  signal shift1 : sl;
54  signal shift2 : sl;
55 
56  attribute IODELAY_GROUP : string;
57  attribute IODELAY_GROUP of U_DELAY : label is IODELAY_GROUP_G;
58 
59 begin
60 
61  -- ADC frame delay
62  U_DELAY : IDELAYE2
63  generic map (
64  DELAY_SRC => "IDATAIN",
65  HIGH_PERFORMANCE_MODE => "TRUE",
66  IDELAY_TYPE => "VAR_LOAD",
67  IDELAY_VALUE => 0, -- Here
68  REFCLK_FREQUENCY => IDELAYCTRL_FREQ_G,
69  SIGNAL_PATTERN => "DATA"
70  )
71  port map (
72  C => sysClk,
73  REGRST => '0',
74  LD => setValid,
75  CE => '0',
76  INC => '1',
77  CINVCTRL => '0',
78  CNTVALUEIN => setDelay,
79  IDATAIN => iData,
80  DATAIN => '0',
81  LDPIPEEN => '0',
82  DATAOUT => dlyData,
83  CNTVALUEOUT => curDelay);
84 
85  U_ISERDES_MASTER : ISERDESE2
86  generic map (
87  DATA_RATE => "DDR",
88  DATA_WIDTH => 14,
89  INTERFACE_TYPE => "NETWORKING",
90  DYN_CLKDIV_INV_EN => "FALSE",
91  DYN_CLK_INV_EN => "FALSE",
92  NUM_CE => 1,
93  OFB_USED => "FALSE",
94  IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
95  SERDES_MODE => "MASTER")
96  port map (
97  Q1 => oData(0),
98  Q2 => oData(1),
99  Q3 => oData(2),
100  Q4 => oData(3),
101  Q5 => oData(4),
102  Q6 => oData(5),
103  Q7 => oData(6),
104  Q8 => oData(7),
105  SHIFTOUT1 => shift1, -- Cascade connection to Slave ISERDES
106  SHIFTOUT2 => shift2, -- Cascade connection to Slave ISERDES
107  BITSLIP => slip, -- 1-bit Invoke Bitslip. This can be used with any
108  -- DATA_WIDTH, cascaded or not.
109  CE1 => '1', -- 1-bit Clock enable input
110  CE2 => '1', -- 1-bit Clock enable input
111  CLK => clkIo, -- Fast Source Synchronous SERDES clock from BUFIO
112  CLKB => clkIoInv, -- Locally inverted clock
113  CLKDIV => clkR, -- Slow clock driven by BUFR
114  CLKDIVP => '0',
115  D => '0',
116  DDLY => dlyData, -- 1-bit Input signal from IODELAYE1.
117  RST => rst, -- 1-bit Asynchronous reset only.
118  SHIFTIN1 => '0',
119  SHIFTIN2 => '0',
120  -- unused connections
121  DYNCLKDIVSEL => '0',
122  DYNCLKSEL => '0',
123  OFB => '0',
124  OCLK => '0',
125  OCLKB => '0',
126  O => open); -- unregistered output of ISERDESE1
127 
128  U_ISERDES_SLAVE : ISERDESE2
129  generic map (
130  DATA_RATE => "DDR",
131  DATA_WIDTH => 14,
132  INTERFACE_TYPE => "NETWORKING",
133  DYN_CLKDIV_INV_EN => "FALSE",
134  DYN_CLK_INV_EN => "FALSE",
135  NUM_CE => 1,
136  OFB_USED => "FALSE",
137  IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
138  SERDES_MODE => "SLAVE")
139  port map (
140  Q1 => open,
141  Q2 => open,
142  Q3 => oData(8),
143  Q4 => oData(9),
144  Q5 => oData(10),
145  Q6 => oData(11),
146  Q7 => oData(12),
147  Q8 => oData(13),
148  SHIFTOUT1 => open,
149  SHIFTOUT2 => open,
150  SHIFTIN1 => shift1, -- Cascade connections from Master ISERDES
151  SHIFTIN2 => shift2, -- Cascade connections from Master ISERDES
152  BITSLIP => slip, -- 1-bit Invoke Bitslip. This can be used with any
153  -- DATA_WIDTH, cascaded or not.
154  CE1 => '1', -- 1-bit Clock enable input
155  CE2 => '1', -- 1-bit Clock enable input
156  CLK => clkIo, -- Fast source synchronous serdes clock
157  CLKB => clkIoInv, -- locally inverted clock
158  CLKDIV => clkR, -- Slow clock driven by BUFR.
159  CLKDIVP => '0',
160  D => '0', -- Slave ISERDES module. No need to connect D, DDLY
161  DDLY => '0',
162  RST => rst, -- 1-bit Asynchronous reset only.
163  -- unused connections
164  DYNCLKDIVSEL => '0',
165  DYNCLKSEL => '0',
166  OFB => '0',
167  OCLK => '0',
168  OCLKB => '0',
169  O => open); -- unregistered output of ISERDESE1
170 
171 end architecture rtl;
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
Ad9249Deserializer.IDELAYCTRL_FREQ_G
IDELAYCTRL_FREQ_Greal := 200.0
Definition: Ad9249Deserializer.vhd:32
Ad9249Deserializer.curDelay
out curDelayslv( 4 downto 0)
Definition: Ad9249Deserializer.vhd:41
Ad9249Deserializer.oData
out oDataslv( 13 downto 0)
Definition: Ad9249Deserializer.vhd:46
Ad9249Deserializer.setDelay
in setDelayslv( 4 downto 0)
Definition: Ad9249Deserializer.vhd:42
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29