How-To Guides

Step-by-step guides for common tasks: integrating the library, porting to new hardware, driving the PyRogue device tree, and cutting a release.

How-To

• Integrate axi-pcie-core as a Git Submodule
  • Add the Submodule
  • Wire it into ruckus.tcl
  • Submodule Version Locks
  • See Also
• Add a New Board
  • Step 1: Create the directory layout
  • Step 2: Write <NewBoard>Core.vhd
  • Step 3: Define AxiPciePkg.vhd constants
  • Step 4: Provision the PCIe IP .xci
  • Step 5: Add .xdc constraints
  • Step 6: Register a HW_TYPE_* constant
  • Step 7: Write the board-level ruckus.tcl
  • Step 8: Optional DDR4 or HBM memory buffer
  • See Also
• Use the PyRogue Device Tree
  • Open the BAR0 Memory Map
  • Configure DMA Streams
  • Instantiate AxiPcieRoot and Start the Tree
  • Read PcieAxiVersion Build Info
  • Simulation: driverPath='sim'
  • See Also
• Release Flow
  • Prerequisites
  • Step 1: Tag Convention
  • Step 2: Tag the Commit and Push
  • What Gets Published
  • How to Consume a Release
  • Safety Checks
  • Migration Note
  • Upstream Schema Reference