iq32bTo16b Entity Reference

Inheritance diagram for iq32bTo16b:

Collaboration diagram for iq32bTo16b:

Entities
iq32bTo16b.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
SYNTH_MODE_G	string := " inferred "
SYNC_STAGES_G	natural range 2 to 8 := 3

Ports
wrClk	in	sl
wrRst	in	sl
validIn	in	sl
overflow	out	sl
dataInI	in	slv ( 31 downto 0 )
dataInQ	in	slv ( 31 downto 0 )
rdClk	in	sl
rdRst	in	sl
validOut	out	sl
underflow	out	sl
dataOutI	out	slv ( 15 downto 0 )
dataOutQ	out	slv ( 15 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/iq32bTo16b.vhd
• protocols/jesd204b/rtl/iq32bTo16b.vhd