i2c_master_byte_ctrl.structural Architecture Reference

Architecture >> i2c_master_byte_ctrl::structural

Processes
shift_register	( clk , nReset )
data_cnt	( clk , nReset )
nxt_state_decoder	( clk , nReset )
shift_register	( clk , nReset )
data_cnt	( clk , nReset )
nxt_state_decoder	( clk , nReset )

Components
i2c_master_bit_ctrl	<Entity i2c_master_bit_ctrl>

Constants
I2C_CMD_NOP	std_logic_vector ( 3 downto 0 ) := " 0000 "
I2C_CMD_START	std_logic_vector ( 3 downto 0 ) := " 0001 "
I2C_CMD_STOP	std_logic_vector ( 3 downto 0 ) := " 0010 "
I2C_CMD_READ	std_logic_vector ( 3 downto 0 ) := " 0100 "
I2C_CMD_WRITE	std_logic_vector ( 3 downto 0 ) := " 1000 "

Types
states	( st_idle , st_start , st_read , st_write , st_ack , st_stop )

Signals
core_cmd	std_logic_vector ( 3 downto 0 )
core_ack	std_logic
core_txd	std_logic
core_rxd	std_logic
al	std_logic
sr	std_logic_vector ( 7 downto 0 )
shift	std_logic
ld	std_logic
go	std_logic
host_ack	std_logic
dcnt	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
cnt_done	std_logic
c_state	states

Instantiations
bit_ctrl	i2c_master_bit_ctrl <Entity i2c_master_bit_ctrl>
bit_ctrl	i2c_master_bit_ctrl <Entity i2c_master_bit_ctrl>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/i2c_master_byte_ctrl.vhd
• protocols/i2c/rtl/i2c_master_byte_ctrl.vhd