XauiGtyUltraScaleWrapper Entity Reference

Inheritance diagram for XauiGtyUltraScaleWrapper:

Collaboration diagram for XauiGtyUltraScaleWrapper:

Entities
XauiGtyUltraScaleWrapper.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
EthMacPkg	Package <EthMacPkg>
XauiPkg	Package <XauiPkg>
vcomponents

Generics
TPD_G	time := 1 ns
EN_WDT_G	boolean := false
STABLE_CLK_FREQ_G	real := 156 . 25E + 6
JUMBO_G	boolean := true
PAUSE_EN_G	boolean := true
ROCEV2_EN_G	boolean := false
EN_AXI_REG_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C

Ports
localMac	in	slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
dmaClk	in	sl
dmaRst	in	sl
dmaIbMaster	out	AxiStreamMasterType
dmaIbSlave	in	AxiStreamSlaveType
dmaObMaster	in	AxiStreamMasterType
dmaObSlave	out	AxiStreamSlaveType
axiLiteClk	in	sl := ' 0 '
axiLiteRst	in	sl := ' 0 '
axiLiteReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiLiteReadSlave	out	AxiLiteReadSlaveType
axiLiteWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiLiteWriteSlave	out	AxiLiteWriteSlaveType
extRst	in	sl := ' 0 '
stableClk	in	sl := ' 0 '
phyClk	out	sl
phyRst	out	sl
phyReady	out	sl
gtTxPreCursor	in	slv ( 19 downto 0 ) := ( others = > ' 0 ' )
gtTxPostCursor	in	slv ( 19 downto 0 ) := ( others = > ' 0 ' )
gtTxDiffCtrl	in	slv ( 19 downto 0 ) := ( others = > ' 1 ' )
gtRxPolarity	in	slv ( 3 downto 0 ) := x " 0 "
gtTxPolarity	in	slv ( 3 downto 0 ) := x " 0 "
gtClkP	in	sl
gtClkN	in	sl
gtClkOut	out	sl
gtTxP	out	slv ( 3 downto 0 )
gtTxN	out	slv ( 3 downto 0 )
gtRxP	in	slv ( 3 downto 0 )
gtRxN	in	slv ( 3 downto 0 )

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The documentation for this design unit was generated from the following file:

• ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd