WatchDogRst.rtl Architecture Reference

Architecture >> WatchDogRst::rtl

Processes
PROCESS_35	( clk )
PROCESS_191	( clk )

Signals
rst	sl := not ( OUT_POLARITY_G )
monInput	sl
cnt	natural range 0 to DURATION_G := 0

Attributes
use_dsp	string
use_dsp	signal is USE_DSP_G

Instantiations
synchronizer_inst	Synchronizer <Entity Synchronizer>
synchronizer_inst	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following files:

• base/general/rtl/WatchDogRst.vhd
• build/SRC_VHDL/surf/WatchDogRst.vhd