UdpEngineTx Entity Reference

Inheritance diagram for UdpEngineTx:

Collaboration diagram for UdpEngineTx:

Entities
UdpEngineTx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
EthMacPkg	Package <EthMacPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SIZE_G	positive := 1
TX_FLOW_CTRL_G	boolean := true
IS_CLIENT_G	boolean := false
PORT_G	PositiveArray := ( 0 = > 8192 )

Ports
obUdpMaster	out	AxiStreamMasterType
obUdpSlave	in	AxiStreamSlaveType
linkUp	out	slv ( SIZE_G- 1 downto 0 )
localMac	in	slv ( 47 downto 0 )
localIp	in	slv ( 31 downto 0 )
remotePort	in	Slv16Array ( SIZE_G- 1 downto 0 )
remoteIp	in	Slv32Array ( SIZE_G- 1 downto 0 )
remoteMac	in	Slv48Array ( SIZE_G- 1 downto 0 )
ibMasters	in	AxiStreamMasterArray ( SIZE_G- 1 downto 0 )
ibSlaves	out	AxiStreamSlaveArray ( SIZE_G- 1 downto 0 )
arpTabPos	out	Slv8Array ( SIZE_G- 1 downto 0 )
arpTabFound	in	slv ( SIZE_G- 1 downto 0 ) := ( others = > ' 0 ' )
arpTabIpAddr	in	Slv32Array ( SIZE_G- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
arpTabMacAddr	in	Slv48Array ( SIZE_G- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
obDhcpMaster	in	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
obDhcpSlave	out	AxiStreamSlaveType
clk	in	sl
rst	in	sl

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The documentation for this design unit was generated from the following file:

• ethernet/UdpEngine/rtl/UdpEngineTx.vhd