UartSem Entity Reference

Inheritance diagram for UartSem:

Collaboration diagram for UartSem:

Entities
UartSem.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
SemPkg	Package <SemPkg>

Generics
TPD_G	time := 1 ns
CLK_FREQ_G	real := 100 . 0E + 6
BAUD_RATE_G	positive := 115200
MEMORY_TYPE_G	string := " block "
FIFO_ADDR_WIDTH_G	positive := 5

Ports
semClk	in	sl
semRst	in	sl
fpgaReload	in	sl := ' 0 '
fpgaReloadAddr	in	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
uartTx	out	sl
uartRx	in	sl

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/sem/rtl/UartSem.vhd