TenGigEthGtyUltraScaleClk.mapping Architecture Reference

Architecture >> TenGigEthGtyUltraScaleClk::mapping

Signals
refClk	sl
refClkCopy	sl
refClock	sl
coreClock	sl
qpllReset	slv ( 1 downto 0 )

Instantiations
ibufds_gte3_inst	ibufds_gte4
bufg_gt_inst	bufg_gt
gtyultrascalequadpll_inst	GtyUltraScaleQuadPll <Entity GtyUltraScaleQuadPll>

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleClk.vhd