TenGigEthGtx7Wrapper.mapping Architecture Reference

Architecture >> TenGigEthGtx7Wrapper::mapping

Signals
phyClock	sl
phyReset	sl
qplllock	sl
qplloutclk	sl
qplloutrefclk	sl
qpllRst	slv ( NUM_LANE_G- 1 downto 0 )
qpllReset	sl

Instantiations
tengigethgtx7clk_inst	TenGigEthGtx7Clk <Entity TenGigEthGtx7Clk>
tengigethgtx7_inst	TenGigEthGtx7 <Entity TenGigEthGtx7>

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd