TenGigEthGthUltraScaleWrapper.mapping Architecture Reference

Architecture >> TenGigEthGthUltraScaleWrapper::mapping

Signals
qplllock	slv ( 1 downto 0 )
qplloutclk	slv ( 1 downto 0 )
qplloutrefclk	slv ( 1 downto 0 )
qpllRst	Slv2Array ( 3 downto 0 ) := ( others = > " 00 " )
qpllReset	slv ( 1 downto 0 )
coreClock	sl
coreReset	sl
qplllock	sl
qplloutclk	sl
qplloutrefclk	sl
qpllRst	slv ( NUM_LANE_G- 1 downto 0 )
qpllReset	sl

Instantiations
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
tengigethgthultrascaleclk_inst	TenGigEthGthUltraScaleClk <Entity TenGigEthGthUltraScaleClk>
tengigethgthultrascale_inst	TenGigEthGthUltraScale <Entity TenGigEthGthUltraScale>
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
tengigethgthultrascaleclk_inst	TenGigEthGthUltraScaleClk <Entity TenGigEthGthUltraScaleClk>
tengigethgthultrascale_inst	TenGigEthGthUltraScale <Entity TenGigEthGthUltraScale>

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The documentation for this design unit was generated from the following files:

• ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd
• ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd