Architecture >> SynchronizerOneShotCntVector::rtl
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comb | ( cntWrDomain , r , tReady , wrRst ) |
seq | ( wrClk , wrRst ) |
PROCESS_70 | ( rdClk , rdRst ) |
comb | ( cntWrDomain , r , tReady , wrRst ) |
seq | ( wrClk , wrRst ) |
PROCESS_170 | ( rdClk , rdRst ) |
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IN_POLARITY_C | slv ( WIDTH_G- 1 downto 0 ) := fillVectorArray ( IN_POLARITY_G ) |
OUT_POLARITY_C | slv ( WIDTH_G- 1 downto 0 ) := fillVectorArray ( OUT_POLARITY_G ) |
SYNTH_CNT_C | slv ( WIDTH_G- 1 downto 0 ) := fillVectorArray ( SYNTH_CNT_G ) |
FIFO_WIDTH_C | positive := CNT_WIDTH_G+ bitSize ( WIDTH_G- 1 ) |
REG_INIT_C | RegType := ( tValid = > ' 0 ' , tData = > ( others = > ' 0 ' ) , index = > 0 ) |
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MySlvArray | ( WIDTH_G- 1 downto 0 ) slv ( CNT_WIDTH_G- 1 downto 0 ) |
The documentation for this design unit was generated from the following files:
- base/sync/rtl/SynchronizerOneShotCntVector.vhd
- build/SRC_VHDL/surf/SynchronizerOneShotCntVector.vhd