SynchronizerEdge.rtl Architecture Reference

Architecture >> SynchronizerEdge::rtl

Processes
comb	( r , rst , syncData )
seq	( clk , rst , syncData )
comb	( r , rst , syncData )
seq	( clk , rst , syncData )

Constants
INIT_C	slv ( STAGES_G- 1 downto 0 ) := ite ( INIT_G = " 0 " , slvZero ( STAGES_G ) , INIT_G )
REG_INIT_C	RegType := ( syncDataDly = > ' 0 ' , dataOut = > ( not OUT_POLARITY_G ) , risingEdge = > ( not OUT_POLARITY_G ) , fallingEdge = > ( not OUT_POLARITY_G ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
syncData	sl

Records
RegType

Instantiations
synchronizer_inst	Synchronizer <Entity Synchronizer>
synchronizer_inst	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SynchronizerEdge.vhd
• build/SRC_VHDL/surf/SynchronizerEdge.vhd