SyncTrigPeriod Entity Reference

Inheritance diagram for SyncTrigPeriod:

Collaboration diagram for SyncTrigPeriod:

Entities
SyncTrigPeriod.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
COMMON_CLK_G	boolean := false
IN_POLARITY_G	sl := ' 1 '
CNT_WIDTH_G	positive := 32

Ports
trigClk	in	sl
trigRst	in	sl
trigIn	in	sl
locClk	in	sl
locRst	in	sl
resetStat	in	sl
period	out	slv ( CNT_WIDTH_G- 1 downto 0 )
periodMax	out	slv ( CNT_WIDTH_G- 1 downto 0 )
periodMin	out	slv ( CNT_WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SyncTrigPeriod.vhd
• build/SRC_VHDL/surf/SyncTrigPeriod.vhd