SyncMinMax.rtl Architecture Reference

Architecture >> SyncMinMax::rtl

Processes
PROCESS_71	( data , gt , ls , r , resetStat , valid , wrRst )
seq	( wrClk , wrRst )
PROCESS_171	( data , gt , ls , r , resetStat , valid , wrRst )
seq	( wrClk , wrRst )

Constants
REG_INIT_C	RegType := ( reset = > ' 1 ' , armed = > ' 0 ' , update = > ' 0 ' , dataIn = > ( others = > ' 0 ' ) , dataMin = > ( others = > ' 0 ' ) , dataMax = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
resetStat	sl
ls	sl
gt	sl
valid	sl
data	slv ( WIDTH_G- 1 downto 0 )
dataMinFeadback	slv ( WIDTH_G- 1 downto 0 )
dataMaxFeadback	slv ( WIDTH_G- 1 downto 0 )

Records
RegType

Instantiations
u_rststat	SynchronizerOneShot <Entity SynchronizerOneShot>
u_lessthan	DspComparator <Entity DspComparator>
u_greaterthan	DspComparator <Entity DspComparator>
u_dataout	SynchronizerFifo <Entity SynchronizerFifo>
u_datamin	SynchronizerFifo <Entity SynchronizerFifo>
u_datamax	SynchronizerFifo <Entity SynchronizerFifo>
u_rststat	SynchronizerOneShot <Entity SynchronizerOneShot>
u_lessthan	DspComparator <Entity DspComparator>
u_greaterthan	DspComparator <Entity DspComparator>
u_dataout	SynchronizerFifo <Entity SynchronizerFifo>
u_datamin	SynchronizerFifo <Entity SynchronizerFifo>
u_datamax	SynchronizerFifo <Entity SynchronizerFifo>

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SyncMinMax.vhd
• build/SRC_VHDL/surf/SyncMinMax.vhd