Sy89297.rtl Architecture Reference

Architecture >> Sy89297::rtl

Processes
comb	( axilReadMaster , axilRst , axilWriteMaster , r )
seq	( axilClk )
comb	( axilReadMaster , axilRst , axilWriteMaster , r )
seq	( axilClk )

Constants

REG_INIT_C

RegType := ( delayA = > ( others = > ' 0 ' ) , delayB = > ( others = > ' 0 ' ) , busy = > ' 0 ' , cnt = > 0 , shiftReg = > ( others = > ' 0 ' ) , sclkEn = > ' 0 ' , sclkCnt = > ( others = > ' 0 ' ) , sckHalfCycle = > ite ( SIMULATION_G , x " 00 " , x " 0F " ) , sclk = > ' 0 ' , sload = > ' 1 ' , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , SEND_DATA_S , SLOAD_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Sy89297.vhd
• devices/Microchip/sy89297/rtl/Sy89297.vhd