StreamPatternTester.rtl Architecture Reference

Architecture >> StreamPatternTester::rtl

Processes
axilComb	( axilR , axilReadMaster , axilWriteMaster , rst , testFailed , testPassed )
axilSeq	( clk )
testProc	( clk )

Constants
AXIL_REG_INIT_C	AxilRegType := ( axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , testChannel = > ( others = > ' 0 ' ) , testPattern = > ( others = > ' 0 ' ) , testDataMask = > ( others = > ' 0 ' ) , testSamples = > ( others = > ' 0 ' ) , testTimeout = > ( others = > ' 0 ' ) , testRequest = > ' 0 ' )

Signals
axilR	AxilRegType := AXIL_REG_INIT_C
axilRin	AxilRegType
dataMux	std_logic_vector ( 31 downto 0 )
dataValidMux	std_logic
testCnt	unsigned ( 31 downto 0 )
testDone	std_logic
testPassed	std_logic
testFailed	std_logic
passCnt	unsigned ( 31 downto 0 )
timeoutCnt	unsigned ( 31 downto 0 )

Records
AxilRegType

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9249/core/StreamPatternTester.vhd