SspLowSpeedDecoder8b10bWrapper.mapping Architecture Reference

Architecture >> SspLowSpeedDecoder8b10bWrapper::mapping

Constants
DATA_WIDTH_C	positive := 16

Signals
dlyConfig	Slv9Array ( NUM_LANE_G- 1 downto 0 )
enUsrDlyCfg	sl
usrDlyCfg	Slv9Array ( NUM_LANE_G- 1 downto 0 )
minEyeWidth	slv ( 7 downto 0 )
lockingCntCfg	slv ( 23 downto 0 )
bypFirstBerDet	sl
lockOnIdle	sl
bitOrder	slv ( 1 downto 0 )
errorMask	slv ( 2 downto 0 )
polarity	slv ( NUM_LANE_G- 1 downto 0 )
errorDet	slv ( NUM_LANE_G- 1 downto 0 )
bitSlip	slv ( NUM_LANE_G- 1 downto 0 )
eyeWidth	Slv9Array ( NUM_LANE_G- 1 downto 0 )
locked	slv ( NUM_LANE_G- 1 downto 0 )
idleCode	slv ( NUM_LANE_G- 1 downto 0 )

Instantiations
u_lane	SspLowSpeedDecoderLane <Entity SspLowSpeedDecoderLane>
u_reg	SspLowSpeedDecoderReg <Entity SspLowSpeedDecoderReg>
u_lane	SspLowSpeedDecoderLane <Entity SspLowSpeedDecoderLane>
u_reg	SspLowSpeedDecoderReg <Entity SspLowSpeedDecoderReg>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SspLowSpeedDecoder8b10bWrapper.vhd
• protocols/ssp/rtl/SspLowSpeedDecoder8b10bWrapper.vhd