SspLowSpeedDecoderLane Entity Reference

Inheritance diagram for SspLowSpeedDecoderLane:

Collaboration diagram for SspLowSpeedDecoderLane:

Entities
SspLowSpeedDecoderLane.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
DATA_WIDTH_G	positive := 10
DLY_STEP_SIZE_G	positive range 1 to 255 := 1

Ports
clk	in	sl
rst	in	sl
deserData	in	slv ( 7 downto 0 )
dlyLoad	out	sl
dlyCfg	out	slv ( 8 downto 0 )
enUsrDlyCfg	in	sl
usrDlyCfg	in	slv ( 8 downto 0 )
minEyeWidth	in	slv ( 7 downto 0 )
lockingCntCfg	in	slv ( 23 downto 0 )
bypFirstBerDet	in	sl
polarity	in	sl
bitOrder	in	slv ( 1 downto 0 )
errorMask	in	slv ( 2 downto 0 )
lockOnIdle	in	sl
errorDet	out	sl
bitSlip	out	sl
eyeWidth	out	slv ( 8 downto 0 )
locked	out	sl
idleCode	out	sl
rxLinkUp	out	sl
rxValid	out	sl
rxData	out	slv ( DATA_WIDTH_G- 1 downto 0 )
rxSof	out	sl
rxEof	out	sl
rxEofe	out	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SspLowSpeedDecoderLane.vhd
• protocols/ssp/rtl/SspLowSpeedDecoderLane.vhd