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SspLowSpeedDecoder10b12bWrapper Entity Reference
Inheritance diagram for SspLowSpeedDecoder10b12bWrapper: Collaboration diagram for SspLowSpeedDecoder10b12bWrapper:Entities | |
| SspLowSpeedDecoder10b12bWrapper.mapping | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
Generics | |
| TPD_G | time := 1 ns |
| SIMULATION_G | boolean := false |
| DLY_STEP_SIZE_G | positive range 1 to 255 := 1 |
| NUM_LANE_G | positive := 1 |
Ports | ||
| deserClk | in | sl |
| deserRst | in | sl |
| deserData | in | Slv8Array ( NUM_LANE_G- 1 downto 0 ) |
| dlyLoad | out | slv ( NUM_LANE_G- 1 downto 0 ) |
| dlyCfg | out | Slv9Array ( NUM_LANE_G- 1 downto 0 ) |
| rxLinkUp | out | slv ( NUM_LANE_G- 1 downto 0 ) |
| rxValid | out | slv ( NUM_LANE_G- 1 downto 0 ) |
| rxData | out | Slv10Array ( NUM_LANE_G- 1 downto 0 ) |
| rxSof | out | slv ( NUM_LANE_G- 1 downto 0 ) |
| rxEof | out | slv ( NUM_LANE_G- 1 downto 0 ) |
| rxEofe | out | slv ( NUM_LANE_G- 1 downto 0 ) |
| axilClk | in | sl |
| axilRst | in | sl |
| axilReadMaster | in | AxiLiteReadMasterType |
| axilReadSlave | out | AxiLiteReadSlaveType |
| axilWriteMaster | in | AxiLiteWriteMasterType |
| axilWriteSlave | out | AxiLiteWriteSlaveType |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/SspLowSpeedDecoder10b12bWrapper.vhd
- protocols/ssp/rtl/SspLowSpeedDecoder10b12bWrapper.vhd
