SspDecoder8b10bTb.sim Architecture Reference

Architecture >> SspDecoder8b10bTb::sim

Processes
WaveGen_Proc
WaveGen_Proc

Constants
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := true

Signals
clkDiv2	sl := ' 0 '
clk	sl := ' 0 '
rst	sl := RST_POLARITY_G
dataIn	slv ( 19 downto 0 ) := ( others = > ' 0 ' )
validIn	sl
dataOut	slv ( 15 downto 0 )
validOut	sl
sof	sl
eof	sl
eofe	sl
dataInEnc	slv ( 15 downto 0 )
dataValidEnc	sl
dataOutEnc	slv ( 19 downto 0 )

Instantiations
stimuli	SspEncoder8b10b <Entity SspEncoder8b10b>
fifo	FifoCascade <Entity FifoCascade>
u_dut	SspDecoder8b10b <Entity SspDecoder8b10b>
stimuli	SspEncoder8b10b <Entity SspEncoder8b10b>
fifo	FifoCascade <Entity FifoCascade>
u_dut	SspDecoder8b10b <Entity SspDecoder8b10b>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SspDecoder8b10bTb.vhd
• protocols/ssp/tb/SspDecoder8b10bTb.vhd