Ssp12b14bTb.tb Architecture Reference

Architecture >> Ssp12b14bTb::tb

Processes
gen
check
gen
check

Constants
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 0 '
RST_ASYNC_G	boolean := true
AUTO_FRAME_G	boolean := true
FLOW_CTRL_EN_G	boolean := false

Signals
clk	sl
rst	sl := RST_POLARITY_G
encValid	sl := ' 0 '
encSof	sl := ' 0 '
encEof	sl := ' 0 '
encDataIn	slv ( 11 downto 0 ) := ( others = > ' 0 ' )
encDataOut	slv ( 13 downto 0 ) := ( others = > ' 0 ' )
decDataIn	slv ( 13 downto 0 ) := ( others = > ' 0 ' )
decDataOut	slv ( 11 downto 0 ) := ( others = > ' 0 ' )
decValid	sl
decSof	sl
decEof	sl
decEofe	sl
decCodeError	sl
decDispError	sl

Instantiations
u_sspencoder12b14b	SspEncoder12b14b <Entity SspEncoder12b14b>
u_sspdecoder12b14b_1	SspDecoder12b14b <Entity SspDecoder12b14b>
u_clkrst_1	ClkRst <Entity ClkRst>
u_sspencoder12b14b	SspEncoder12b14b <Entity SspEncoder12b14b>
u_sspdecoder12b14b_1	SspDecoder12b14b <Entity SspDecoder12b14b>
u_clkrst_1	ClkRst <Entity ClkRst>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Ssp12b14bTb.vhd
• protocols/ssp/tb/Ssp12b14bTb.vhd