SsiFrameLimiter.rtl Architecture Reference

Architecture >> SsiFrameLimiter::rtl

Processes
comb	( mAxisRst , r , rxMaster , txSlave )
seq	( mAxisClk , mAxisRst )
comb	( mAxisRst , r , rxMaster , txSlave )
seq	( mAxisClk , mAxisRst )

Constants
TIMEOUT_C	natural := getTimeRatio ( MAXIS_CLK_FREQ_G* TIMEOUT_G , 1 . 0 )
SLAVE_FIFO_C	boolean := ite ( SLAVE_FIFO_Gor ( COMMON_CLK_G = false ) or ( SLAVE_READY_EN_G = false ) , true , false )
REG_INIT_C	RegType := ( cnt = > 0 , timer = > 0 , rxSlave = > AXI_STREAM_SLAVE_INIT_C , txMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , MOVE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
rxMaster	AxiStreamMasterType
rxSlave	AxiStreamSlaveType
txMaster	AxiStreamMasterType
txSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_resize_ob	AxiStreamGearbox <Entity AxiStreamGearbox>
fifo_rx	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
fifo_tx	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_resize_ob	AxiStreamGearbox <Entity AxiStreamGearbox>
fifo_rx	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
fifo_tx	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiFrameLimiter.vhd
• protocols/ssi/rtl/SsiFrameLimiter.vhd