SsiAxiLiteMaster.rtl Architecture Reference

Architecture >> SsiAxiLiteMaster::rtl

Processes
comb	( axiLiteRst , mAxiLiteReadSlave , mAxiLiteWriteSlave , mFifoAxisCtrl , r , sFifoAxisMaster )
seq	( axiLiteClk , axiLiteRst )
comb	( axiLiteRst , mAxiLiteReadSlave , mAxiLiteWriteSlave , mFifoAxisCtrl , r , sFifoAxisMaster )
seq	( axiLiteClk , axiLiteRst )

Constants
SLAVE_FIFO_SSI_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 4 , TKEEP_COMP_C )
MASTER_FIFO_SSI_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 4 , TKEEP_COMP_C )
REG_INIT_C	RegType := ( echo = > ( others = > ' 0 ' ) , address = > ( others = > ' 0 ' ) , rdSize = > ( others = > ' 0 ' ) , rdCount = > ( others = > ' 0 ' ) , timer = > ( others = > ' 1 ' ) , state = > S_IDLE_C , timeout = > ' 0 ' , fail = > ' 0 ' , mAxiLiteWriteMaster = > AXI_LITE_WRITE_MASTER_INIT_C , mAxiLiteReadMaster = > AXI_LITE_READ_MASTER_INIT_C , sFifoAxisSlave = > AXI_STREAM_SLAVE_INIT_C , mFifoAxisMaster = > AXI_STREAM_MASTER_INIT_C )

Types
StateType	( S_IDLE_C , S_ADDR_C , S_WRITE_C , S_WRITE_AXI_C , S_READ_SIZE_C , S_READ_C , S_READ_AXI_C , S_STATUS_C , S_DUMP_C )

Signals
sFifoAxisMaster	AxiStreamMasterType
sFifoAxisSlave	AxiStreamSlaveType
mFifoAxisMaster	AxiStreamMasterType
mFifoAxisSlave	AxiStreamSlaveType
mFifoAxisCtrl	AxiStreamCtrlType
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

Instantiations
slaveaxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
masteraxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
slaveaxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
masteraxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiAxiLiteMaster.vhd
• protocols/ssi/rtl/SsiAxiLiteMaster.vhd