SrpV0AxiLiteWrapper Entity Reference

Inheritance diagram for SrpV0AxiLiteWrapper:

Collaboration diagram for SrpV0AxiLiteWrapper:

Entities
SrpV0AxiLiteWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
EN_32BIT_ADDR_G	boolean := false

Ports
AXIS_ACLK	in	std_logic
AXIS_ARESETN	in	std_logic
S_AXIS_TVALID	in	std_logic
S_AXIS_TDATA	in	std_logic_vector ( 31 downto 0 )
S_AXIS_TKEEP	in	std_logic_vector ( 3 downto 0 )
S_AXIS_TLAST	in	std_logic
S_AXIS_TUSER	in	std_logic_vector ( 1 downto 0 )
S_AXIS_TREADY	out	std_logic
M_AXIS_TVALID	out	std_logic
M_AXIS_TDATA	out	std_logic_vector ( 31 downto 0 )
M_AXIS_TKEEP	out	std_logic_vector ( 3 downto 0 )
M_AXIS_TLAST	out	std_logic
M_AXIS_TUSER	out	std_logic_vector ( 1 downto 0 )
M_AXIS_TREADY	in	std_logic
M_AXIL_AWADDR	out	std_logic_vector ( 31 downto 0 )
M_AXIL_AWPROT	out	std_logic_vector ( 2 downto 0 )
M_AXIL_AWVALID	out	std_logic
M_AXIL_AWREADY	in	std_logic
M_AXIL_WDATA	out	std_logic_vector ( 31 downto 0 )
M_AXIL_WSTRB	out	std_logic_vector ( 3 downto 0 )
M_AXIL_WVALID	out	std_logic
M_AXIL_WREADY	in	std_logic
M_AXIL_BRESP	in	std_logic_vector ( 1 downto 0 )
M_AXIL_BVALID	in	std_logic
M_AXIL_BREADY	out	std_logic
M_AXIL_ARADDR	out	std_logic_vector ( 31 downto 0 )
M_AXIL_ARPROT	out	std_logic_vector ( 2 downto 0 )
M_AXIL_ARVALID	out	std_logic
M_AXIL_ARREADY	in	std_logic
M_AXIL_RDATA	in	std_logic_vector ( 31 downto 0 )
M_AXIL_RRESP	in	std_logic_vector ( 1 downto 0 )
M_AXIL_RVALID	in	std_logic
M_AXIL_RREADY	out	std_logic

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The documentation for this design unit was generated from the following file:

• protocols/srp/wrappers/SrpV0AxiLiteWrapper.vhd