SlvDelayFifo.rtl Architecture Reference

Architecture >> SlvDelayFifo::rtl

Processes
comb	( delay , fifoReadoutData , fifoReadoutTime , fifoValid , r , rst )
seq	( clk , rst )
comb	( delay , fifoReadoutData , fifoReadoutTime , fifoValid , r , rst )
seq	( clk , rst )

Constants
FIFO_MIN_LAT_C	positive := 4
FIFO_WIDTH_C	natural := DELAY_BITS_G+ DATA_WIDTH_G
REG_INIT_C	RegType := ( timeNow = > ( others = > ' 0 ' ) , readoutTime = > ( others = > ' 0 ' ) , fifoRdEn = > ' 0 ' , outputData = > ( others = > ' 0 ' ) , outputValid = > ' 0 ' )

Subtypes
DATA_FIELD_C	natural range DATA_WIDTH_G- 1 downto 0
DELAY_FIELD_C	natural range ( DELAY_BITS_G+ DATA_WIDTH_G ) - 1 downto DATA_WIDTH_G

Signals
r	RegType := REG_INIT_C
rin	RegType
fifoReadoutTime	slv ( DELAY_BITS_G- 1 downto 0 )
fifoReadoutData	slv ( DATA_WIDTH_G- 1 downto 0 )
fifoValid	sl
fifoRdEn	sl
fifoDin	slv ( FIFO_WIDTH_C- 1 downto 0 )
fifoDout	slv ( FIFO_WIDTH_C- 1 downto 0 )

Records
RegType

Instantiations
u_delayfifo	Fifo <Entity Fifo>
u_delayfifo	Fifo <Entity Fifo>

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The documentation for this design unit was generated from the following files:

• base/delay/rtl/SlvDelayFifo.vhd
• build/SRC_VHDL/surf/SlvDelayFifo.vhd