SlvDelayFifo Entity Reference

Inheritance diagram for SlvDelayFifo:

Collaboration diagram for SlvDelayFifo:

Entities
SlvDelayFifo.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
DATA_WIDTH_G	positive := 1
DELAY_BITS_G	positive := 64
FIFO_ADDR_WIDTH_G	positive := 7
FIFO_MEMORY_TYPE_G	string := " block "

Ports
clk	in	sl
rst	in	sl
delay	in	slv ( DELAY_BITS_G- 1 downto 0 )
inputData	in	slv ( DATA_WIDTH_G- 1 downto 0 )
inputValid	in	sl
inputAFull	out	sl
outputData	out	slv ( DATA_WIDTH_G- 1 downto 0 )
outputValid	out	sl

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The documentation for this design unit was generated from the following files:

• base/delay/rtl/SlvDelayFifo.vhd
• build/SRC_VHDL/surf/SlvDelayFifo.vhd