SizedFIFO.rtl Architecture Reference

Architecture >> SizedFIFO::rtl

Processes
PROCESS_123	( CLK )
PROCESS_124	( CLK )
PROCESS_125	( CLK )

Constants
P2DEPTH2_C	natural := ite ( ( P2DEPTH_G> = 2 ) , P2DEPTH_G- 2 , 0 )
DEPTH_LESS2_C	unsigned ( P3CNTR_WIDTH_G- 1 downto 0 ) := to_unsigned ( P2DEPTH2_C , P3CNTR_WIDTH_G )

Types
RingArrayType	( 0 to P2DEPTH2_C ) slv ( P1WIDTH_G- 1 downto 0 )

Signals
headPtr	unsigned ( P3CNTR_WIDTH_G- 1 downto 0 )
tailPtr	unsigned ( P3CNTR_WIDTH_G- 1 downto 0 )
nextHead	unsigned ( P3CNTR_WIDTH_G- 1 downto 0 )
nextTail	unsigned ( P3CNTR_WIDTH_G- 1 downto 0 )
notFull	sl
ringEmpty	sl
hasOData	sl
outReg	slv ( P1WIDTH_G- 1 downto 0 )
ringArr	RingArrayType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/blue-lib/SizedFIFO.vhd