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SinCosTaylor.rtl Architecture Reference
Architecture >> SinCosTaylor::rtl

Processes

seq  ( clk )

Constants

LUT_LATENCY_C  integer := 4 + ite ( REG_IN_G , 1 , 0 )
MULT_LATENCY_C  integer := 4
ADD_LATENCY_C  integer := 1
TOT_LATENCY_C  integer := LUT_LATENCY_C+ MULT_LATENCY_C+ ADD_LATENCY_C
TRUN_BITS_C  integer := PHASE_WIDTH_G- INT_PHASE_WIDTH_G
M_PI_C  sfixed ( 2 downto - 15 ) := to_sfixed ( MATH_PI , 2 , - 15 )

Signals

phaseTrun  unsigned ( phaseIn ' high downto phaseIn ' high- INT_PHASE_WIDTH_G+ 1 ) := ( others = > ' 0 ' )
phaseRemainder  sfixed ( 1 - INT_PHASE_WIDTH_G downto 1 - phaseIn ' length ) := ( others = > ' 0 ' )
phaseRad  sfixed ( phaseRemainder ' high+ 2 downto phaseRemainder ' high+ 2 - 17 ) := ( others = > ' 0 ' )
sinCosTrun  cfixed ( re ( sinCosOut.re ' range ) , im ( sinCosOut.im ' range ) )
sinCosTrunDelay  cfixed ( re ( sinCosOut.re ' range ) , im ( sinCosOut.im ' range ) )
sinPiInt  sfixed ( sinCosOut.re ' range )
cosPiInt  sfixed ( sinCosOut.re ' range )
sinCosCorr  cfixed ( re ( sinCosOut.re ' range ) , im ( sinCosOut.im ' range ) )
slvDelayIn  slv ( USER_WIDTH_G downto 0 )
slvDelayOut  slv ( USER_WIDTH_G downto 0 )

Instantiations

u_match_tot_delay  SlvFixedDelay <Entity SlvFixedDelay>
u_sin_cos_lut  SinCosLut <Entity SinCosLut>
u_match_delay  cfixedDelay <Entity cfixedDelay>
u_mult_pi  sfixedMult <Entity sfixedMult>
u_mult_cos  sfixedMult <Entity sfixedMult>
u_mult_sin  sfixedMult <Entity sfixedMult>

The documentation for this design unit was generated from the following file: