cfixedDelay Entity Reference

Inheritance diagram for cfixedDelay:

Collaboration diagram for cfixedDelay:

Entities
cfixedDelay.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
fixed_pkg
StdRtlPkg	Package <StdRtlPkg>
ComplexFixedPkg	Package <ComplexFixedPkg>

Generics
TPD_G	time := 1 ns
XIL_DEVICE_G	string := " ULTRASCALE_PLUS "
USER_WIDTH_G	integer := 0
DELAY_STYLE_G	string := " srl_reg "
DELAY_G	integer := 256

Ports
clk	in	sl
validIn	in	sl := ' 0 '
userIn	in	slv ( USER_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
din	in	cfixed
validOut	out	sl
userOut	out	slv ( USER_WIDTH_G- 1 downto 0 )
dout	out	cfixed

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The documentation for this design unit was generated from the following file:

• dsp/xilinx/fixed/CfixedDelay.vhd