Si5345 Entity Reference

Inheritance diagram for Si5345:

Collaboration diagram for Si5345:

Entities
Si5345.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
MEMORY_INIT_FILE_G	string := " none "
CLK_PERIOD_G	real := ( 1 . 0 / 156 . 25E + 6 )
SPI_SCLK_PERIOD_G	real := ( 1 . 0 / 10 . 0E + 6 )

Ports
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
booting	out	sl
coreRst	out	sl
coreSclk	out	sl
coreSDin	in	sl
coreSDout	out	sl
coreCsb	out	sl

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The documentation for this design unit was generated from the following file:

• devices/Silabs/si5345/rtl/Si5345.vhd