SelectioDeserLaneUltraScale.mapping Architecture Reference

Architecture >> SelectioDeserLaneUltraScale::mapping

Signals
rx	sl
rxDly	sl
clkx4L	sl

Instantiations
u_ibufds	ibufds
u_delay	Idelaye3Wrapper <Entity Idelaye3Wrapper>
u_iserdes	iserdese3

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The documentation for this design unit was generated from the following file:

• xilinx/UltraScale/general/rtl/SelectioDeserLaneUltraScale.vhd