SaltTx.rtl Architecture Reference

Architecture >> SaltTx::rtl

Processes
comb	( mMaster , r , rst , rxMaster , sSlave , txSlave )
seq	( clk )

Constants

REG_INIT_C

RegType := ( flushBuffer = > ' 1 ' , sof = > ' 0 ' , eof = > ' 0 ' , eofe = > ' 0 ' , txPktSent = > ' 0 ' , txEofeSent = > ' 0 ' , seqCnt = > ( others = > ' 0 ' ) , tDest = > ( others = > ' 0 ' ) , cnt = > ( others = > ' 0 ' ) , size = > ( others = > ' 0 ' ) , length = > ( others = > ' 0 ' ) , checksum = > ( others = > ' 0 ' ) , txMaster = > AXI_STREAM_MASTER_INIT_C , rxSlave = > AXI_STREAM_SLAVE_INIT_C , sMaster = > AXI_STREAM_MASTER_INIT_C , mSlave = > AXI_STREAM_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , BUFFER_S , PREAMBLE_S , SFD_S , HEADER_S , LENGTH_S , MOVE_S , CHECKSUM_S , FOOTER_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
rxMaster	AxiStreamMasterType
rxSlave	AxiStreamSlaveType
sMaster	AxiStreamMasterType
sSlave	AxiStreamSlaveType
mMaster	AxiStreamMasterType
mSlave	AxiStreamSlaveType
txMaster	AxiStreamMasterType
txSlave	AxiStreamSlaveType

Records
RegType

Instantiations
fifo_rx	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
datagram_buffer	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_txresize	SaltTxResize <Entity SaltTxResize>

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The documentation for this design unit was generated from the following file:

• protocols/salt/rtl/SaltTx.vhd