SaltRx.rtl Architecture Reference

Architecture >> SaltRx::rtl

Processes
comb	( r , rst , rxData , rxEn , rxErr , rxLinkUp , txSlave )
seq	( clk )

Constants

REG_INIT_C

RegType := ( rxPktRcvd = > ' 0 ' , rxErrDet = > ' 0 ' , sof = > ' 1 ' , eofe = > ' 0 ' , align = > ' 0 ' , seqCnt = > ( others = > ' 0 ' ) , tDest = > ( others = > ' 0 ' ) , tKeep = > ( others = > ' 0 ' ) , size = > ( others = > ' 0 ' ) , cnt = > ( others = > ' 0 ' ) , checksum = > ( others = > ' 0 ' ) , alignCnt = > 0 , dly = > ( others = > AXI_STREAM_MASTER_INIT_C ) , txMaster = > AXI_STREAM_MASTER_INIT_C , rxMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , LENGTH_S , MOVE_S , CHECKSUM_S , DONE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
txMaster	AxiStreamMasterType
txSlave	AxiStreamSlaveType

Records
RegType

Instantiations
fifo_tx	SsiFifo <Entity SsiFifo>

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The documentation for this design unit was generated from the following file:

• protocols/salt/rtl/SaltRx.vhd