SaciSlaveWrapper.rtl Architecture Reference

Architecture >> SaciSlaveWrapper::rtl

Signals
saciSlaveRstL	sl
exec	sl
ack	sl
readL	sl
cmd	slv ( 6 downto 0 )
addr	slv ( 11 downto 0 )
wrData	slv ( 31 downto 0 )
rdData	slv ( 31 downto 0 )
saciRspInt	sl

Instantiations
sacislave_i	SaciSlave <Entity SaciSlave>
sacislaveram_1	SaciSlaveRam <Entity SaciSlaveRam>
sacislave_i	SaciSlave <Entity SaciSlave>
sacislaveram_1	SaciSlaveRam <Entity SaciSlaveRam>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciSlaveWrapper.vhd
• protocols/saci/saci1/sim/SaciSlaveWrapper.vhd