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SaciSlaveRam Entity Reference
Inheritance diagram for SaciSlaveRam:Entities | |
| SaciSlaveRam.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
| StdRtlPkg | Package <StdRtlPkg> |
Ports | ||
| saciClkOut | in | sl |
| exec | in | sl |
| ack | out | sl |
| readL | in | sl |
| cmd | in | slv ( 6 downto 0 ) |
| addr | in | slv ( 11 downto 0 ) |
| wrData | in | slv ( 31 downto 0 ) |
| rdData | out | slv ( 31 downto 0 ) := ( others = > ' 0 ' ) |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/SaciSlaveRam.vhd
- protocols/saci/saci1/sim/SaciSlaveRam.vhd
